Abstract: A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Addresses are compared with programmed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that programmed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. The clock stopping signal is removed or inhibited when primary or secondary activity is detected or when nap mode is terminated by timeout.

Abstract: An information processing system comprises a plurality of information processing devices; and a fault-tolerant power distribution system comprising a plurality N+1, wherein N is greater than 1, removable power supplies for providing power to the system, N power supplies being sufficient to provide power to the plurality of devices; and a plurality M removable power distribution units for connecting the power supplies to the devices, the connection of the power supplies with the power distribution units being configured such that on removal of either of the units, the remaining unit is still connected to N of the power supplies to thereby maintain power to the system.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The multimedia bus is preferably time sliced wherein time slices or time slots are allocated in proportion to the required bandwidth. Each multimedia device includes programmable time slotting logic which determines the appropriate time slot. In one embodiment, the time slices are each a constant size and a number of the equal sized time slots are allocated to respective data streams in proportion to the required bandwidth. Alternatively, the time slots are dynamically sized or allocated to data streams in proportion to the required bandwidth.

Abstract: A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.

Abstract: In a host computer which controls a peripheral device such as a printer, information is recognized which indicates a status of the peripheral device and a suitable time interval is selected to transmit on an interrogation command to demand the status of the peripheral device to the peripheral device. The time interval is selected based on the status of the peripheral device, and may be selected from among several time intervals set up in advance, for example, in a table.

Abstract: A network system, in which a plurality of computers are connected to a network at a plurality of connectors, and a plurality of address conversion devices are provided in correspondence to the connectors. In each address conversion device, a fixed address on the network corresponding to each address conversion device is stored, while a computer address of one computer connected at one connector corresponding to each address conversion device is acquired and stored. Then, a source address contained in a message transmitted from that one computer to the network given in terms of the computer address is converted into the stored fixed address, while a destination address contained in a message transmitted from the network to that one computer given in terms of the fixed address is converted into the stored computer address.

Abstract: A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. A method for configuring the bus includes detecting connection and disconnection of a peripheral device to the bus. In the method, a last peripheral device on the bus is assigned the second status and all other peripheral devices on the bus are assigned the first status. Each peripheral device assigned the first status is configured to pass therethrough an interrupt signal on the bus. The last peripheral device is configured to invert an interrupt signal on the bus from a peripheral device that is newly attached to the bus. A peripheral device newly connected to the bus generates an interrupt signal that is inverted by the last peripheral device and transmitted over the bus to a host computer for the bus.

Abstract: A system and method for choosing communication pathways for data transfers on a computer chip based on desired latency and bandwidth characteristics. On a computer chip including a network of resources, those resources are allocated based upon the needs of the various components of the computer chip. Typical resources on the computer chip include a first bus with a plurality of data lines and control lines and having first bandwidth and latency characteristics, a second bus with a plurality of data lines and control lines having second bandwidth and latency characteristics, and a plurality of devices coupled to the first bus and second bus. Each device includes interface logic for accessing and performing transfers on the first and second buses. Each device is operable to select either the first or second bus depending on desired bandwidth and latency characteristics. Normally the first bandwidth is greater than the second bandwidth.

Abstract: A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the system is more loosely coupled with only masters being ordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on said split-transaction bus are monitored. When a combination of transactions would, if a predetermined further transaction were to begin, result in deadlock, this condition is detected. In the more tightly coupled system, the predetermined further transaction, if it is requested, is refused, thereby avoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case, reorder the transactions and avoid deadlock without killing any transaction.

Abstract: A serial data bus with a two-wire line and a plurality of bus nodes for the exchange of data messages in both directions between the bus nodes and a central unit connected to the bus and for the current supply of the bus nodes. Conflicts between data messages that appear simultaneously are resolved on the basis of the priority thereof. The bus is constructed in the manner of a multi-master system in which each bus and the central unit is a master, and the central unit provides the bus timing and controls the synchronization of the bus. Each bit transmission is divided up into a positive and a negative phase, the current supply of the bus nodes being effected in the positive phase and the data transmission being effected in the negative phase.The bus is preferably used for a hazard-detection system wherein the bus nodes comprise a micro-controller and either are constituted by special detectors with integrated bus or comprise an interface for the connection of the detectors.

Abstract: The present invention relates to a computer network having a host computer and a plurality of user computers connected to the host computer by a computer network wherein the host computer can send a signal to inhibit any or all the user computers from completely powering down. More particularly, the present invention relates to a computer that can be inhibited from powering down when a user presses a power button. The computer may enter a standby state instead of powering down. Furthermore, the computer may inform the user that it is going to go into a standby state at a predetermined event after a power down inhibit signal is received from a host computer.

Abstract: A system for reducing power consumption of a computer peripheral device connected to a host computer during periods of inactivity of the host computer has a dedicated input for initiating power management operations. When the dedicated input is sensed a timer is started and a power management command is sent to the peripheral device, initiating a reduced-power mode other than off. In a preferred embodiment the system also starts a timer when the dedicated input is sensed, and after a predetermined time a second power management command is sent triggering a second reduced-power mode for the peripheral. The system is adapted to peripheral devices such as video displays and printers.

Abstract: A dynamic hibernation time apparatus monitors and ensures that battery packs in a computer system have sufficient energy capacity to sustain a proper saving of the hibernation file into the hard disk drive. The invention determines the memory size of the computer and adds the storage space needed to store the chip register contents to arrive at the determination of the hibernation file size. Next, the time necessary to save the hibernation file on the disk data storage device and the hibernation energy required to operate the disk data storage device to completely save the hibernation file are determined. When the battery capacity drops within a range of the previously computed hibernation energy, a warning message is generated at the user and the hibernation file is saved. The computer is shut down after the hibernation file has been properly saved.

Abstract: An electronic circuit apparatus is provided for electronic circuits and devices, comprising a component disk drive, a disk controller, and a programmable interface for dynamically adapting the component drive to communicate over a predetermined bus architecture to an external application. The interface is programmed by the disk controller using one of a library of microcode sets stored on the component drive. Alternatively, a microprocessor independent of the disk controller programs the interface from microcode stored in solid state memory. In an alternative embodiment, the apparatus further comprises an application circuit and the programmable interface adapts the component drive for use by the circuit. In another embodiment, the apparatus comprises a subcircuit that communicates with an external application over a predetermined bus architecture, and the programmable interface adapts the subcircuit for such communication.

Abstract: Disclosed is a method for transferring data between at least one direct access storage device in a media console and devices in a system unit. The system unit is separate from the media console and includes a microprocessor coupled to a local bus and an expansion bus. An electrical connector having one end coupled to the media console and another end coupled to the system unit is used for electrically connecting device(s) in the console to devices in the system unit. The method includes the steps of monitoring the expansion bus with a first interface in the system unit to determine when a bus cycle initiated by a device in the system unit is directed to the direct access storage device and transferring data from the expansion bus to the direct access storage device via the electrical connector and a second interface in the console when a bus cycle is directed to the direct access storage device.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined subelement of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: Several graphics processing elements are interconnected in a ring using a plurality of individual busses. Each bus interconnects a pair of the graphics processing elements and includes a like group of signal lines for transferring graphics command signals and information signals between graphics processing elements in the ring.

Abstract: An interface circuit included in a ring interconnected group of processing elements includes a backup FIFO to temporarily store information received by the interface circuit when it receives an indication that it temporarily should not forward information to the next processing element in the ring. The interface circuit can receive such an indication, for example, when it receives a signal from the downstream processing element in the ring indicating that the downstream circuit is unable to receive information, or when it receives an information packet requesting a read from the core of the processing element. When the interface circuit receives such an indication, it de-asserts an outgoing ready signal to the upstream processing element in the ring, which should cause the upstream processing element to stop sending information.

Abstract: In a microcomputer including a central processing unit (CPU), a user mode interrupt control circuit for generating a user mode interrupt request signal and transmitting the user mode interrupt request signal to the CPU, and a supervisor mode interrupt control circuit for generating a supervisor interrupt request signal, a selector circuit is connected to the CPU, the user mode interrupt control circuit and the supervisor mode interrupt control circuit. When the selector circuit is in a first state, the supervisor mode interrupt request signal is transmitted from the supervisor mode interrupt control circuit directly to the CPU. When the selector is in a second state, the supervisor mode interrupt request signal is transmitted from the supervisor mode interrupt control circuit via the user mode interrupt control circuit to the CPU.

Abstract: An interface circuit receives both priority and non-priority information non-concurrently on a shared input bus during a first clock cycle and transmits the information received during the first clock cycle non-concurrently to a shared output bus during a second clock cycle following the first clock cycle. The received information includes status data identifying it as being either priority or non-priority information. All received information is provided to an external circuit via either a priority information path or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When the interface circuit is unable to transmit information, received information is backed up into either a priority or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information.