Abstract: A system and method for multiplexing the data outputs of multiple devices to a data bus using variable size multiplexers that do not require an even 2.sup.N number of inputs. This enables logical groupings of like registers to be more easily and more efficiently multiplexed together. The multiplexing system includes a plurality of registers wherein each register supplies eight bits of data to an eight-bit data bus. Register decode logic receives addresses from the bus and outputs a plurality of register select signals that select the registers during write cycles. The register select signals are also coupled with the outputs of each respective register to form an internal 9-bit bus output from each of the registers. The 9-bit bus internal output from each of the plurality of registers are coupled through one or more layers of multiplexing logic to provide an output to the eight-bit data bus. Instead of using standard 2.sup.N multiplexers with N select lines and 2.sup.

Abstract: A dynamic hibernation time apparatus monitors and ensures that battery packs in a computer system have sufficient energy capacity to sustain a proper saving of the hibernation file into the hard disk drive. The invention determines the memory size of the computer and adds the storage space needed to store the chip register contents to arrive at the determination of the hibernation file size. Next, the time necessary to save the hibernation file on the disk data storage device and the hibernation energy required to operate the disk data storage device to completely save the hibernation file are determined. When the battery capacity drops within a range of the previously computed hibernation energy, a warning message is generated at the user and the hibernation file is saved. The computer is shut down after the hibernation file has been properly saved.

Abstract: A circuit to reduce the power consumption of a microprocessor includes activity monitor circuitry to generate an activity signal in response to a low activity operational state of the microprocessor. A clock controller connected to the activity monitor circuitry produces a periodic clock gating signal from the activity signal. Clock gating circuits intermittently apply the internal clock signal to the microprocessor logic circuitry in response to the periodic clock gating signal.

Abstract: A SCSI expansion device receives a first SCSI identifier and logical unit number from a first SCSI bus for identifying a first SCSI peripheral. The SCSI expansion device converts the first SCSI identifier and logical unit number to a second SCSI identifier and logical unit number and represents the first SCSI peripheral to external devices coupled to a second SCSI bus with the second SCSI identifier and logical unit number.

Abstract: Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.

Abstract: A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

Abstract: A RF data communications system for remotely collecting data and a method of developing applications for such a system are provided. The RF data communications system preferably has a first computer including at least a first microprocessor, a first screen display, and a first data screen file positioned representing a first predetermined screen display format. A first RF data transceiver is positioned in electrical communication with the first microprocessor of the first computer for transmitting and receiving RF data, and a second RF data transceiver is positioned remote from the first RF data transceiver and the first computer for transmitting RF data to and receiving RF data from the first RF data transceiver. A second computer is positioned in electrical communication with the second RF data transceiver and remote from the first computer.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: Method and apparatus for detecting the presence of a semi-compliant PCI device in a secondary expansion slot of a PC and instructing the user to reinsert the device into one of the primary slots are disclosed. In one embodiment, upon detection of a semi-compliant PCI device in a secondary slot, a video image instructing the user to reinsert the device into one of the primary slots is displayed on a display of the PC. Operation remains suspended until the device is relocated to a primary slot. In a presently preferred embodiment, a hardware enhancement to a PCI-to-PCI bridge connecting a primary PCI bus to a secondary BCI bus enables the device to operate flawlessly on the secondary PCI bus, such that the user remains unaware of the otherwise undesirable situation.

Abstract: A microprocessor which is constructed to output outside a pipeline flash signal in response to a branch caused by a conditional branch instruction being to be taken, includes a decoder unit decoding and producing decoded information of each of instructions to be executed, the decoder unit further producing branch conduction information designated by the conditional branch instruction, a latch latching the decoded information in response to a write-enable signal and outputting it in response to a read-enable signal, an execution unit performing a data processing operation in response to the decoded information from the latch and including a status word register for temporarily storing an execution state thereof, and a branch detection unit for detecting whether or not a branch is to be taken in response to the branch condition information and the execution state and responding to the write-enable signal to produce a detection signal when the branch is detected to be taken, the pipeline flash signal being there

Abstract: A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

Abstract: An arbitrator for selectively permitting access to a common resource by a priority device and two non-priority devices, includes a priority request reception device for receiving a priority request to access the resource by the priority device; two second request reception devices for receiving non-priority requests to access the resource by the two non-priority devices; a prioritizer coupled to receive indications of times when the priority request reception device receives the priority request and when the two non-priority request reception devices receive the non-priority requests, with the prioritizer permitting access to the resource by the priority device and non-priority device in a predetermined order.

Abstract: A method for automated testing of both new and revised computer application programs which use a Graphical User Interface (GUI). Simulated user events such as keyboard or mouse actions are automatically input into the GUI interface. The GUI is then monitored to observes the changes to the GUI in response to the input. The invention comprises a test script which is written in a high level programming language, a test executive which executes the test script, and a test driver which provides the interface to the GUI. The test script is directed towards operation on logical objects, instead of GUI-specific references. The primary responsibility of the test executive is to convert GUI-independent references into GUI-specific references. The test driver takes the GUI-specific references from the test executive and performs the actual interface to the GUI objects.

Abstract: In order to connect a computer comprising plural redundant processors to at least one digital data transfer bus, the interfacing device embodying the invention comprises: a means for synchronizing and comparing the transmission and reception requests respectively transmitted by the processors, and for triggering processing of a request when the latter has been transmitted by all the processors, a means for transferring the data blocks to be transmitted or received between a controller of said bus and the respective working memories of the processors, and a means for triggering the transfer of a data block if the latter is simultaneously at the output of all the processors, from one of the working memories to said bus controller, with a view to transmission thereof on said bus.

Abstract: A method for bit cell determination and timeout detection for an Apple Desktop Bus, using a counter clocked by a clock generator, according to the steps of: At the start of a bit cell, loading an initial value into the counter and enabling the counter to count down as clocked by the clock generator. Counting down until a low to high transition in the input ADB signal is detected or a terminal count is reached, such that if the low to high transition transition is detected, then enabling the counter to count up, else if the terminal count is reached, then indicating a timeout condition. If the counter is enabled to count up, then counting up until a high to low transition in the input ADB signal is detected or the terminal count is reached, such that if the high to low transition is detected, then stopping the counter and reading a final value to determine the bit cell value, else if the terminal count is reached, then indicating a timeout condition.

Abstract: A computer system for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "aging factor" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral was last granted ownership of the bus. An arbitration control unit is coupled to the aging factor counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the aging signal corresponding to the device.

Abstract: The system resources in a computer system having a multi-level, hierarchical bus structure are allocated by determining the address resource requirement of the devices and lower level PCI-PCI bridges, if any, subordinate to every higher level bridge by receiving address resource requirement information from each device and each lower level bridge, if any. Then, the address value of resource address requirement of the devices and lower level bridges requiring specific address allocation are sorted in an ascending order. Next, the size of resource address requirement of the devices and lower level bridges with non-specified address allocation is sorted in an descending order. Finally, the sorted list is grouped by an first fit algorithm to determine the resource allocation for each device within the bus hierarchy.

Abstract: A system resource enable apparatus for enabling operations on a system resource including a register representing current and future operations on the resource, a pattern generator that applies a pattern corresponding to a requested resource operation to each of a plurality of requests for resource operations in a queue, compare logic that determines for each of the plurality of requests if the request will conflict with other resource operations by comparing the pattern applied to the request with the register, priority grant logic that grants priority to a request in the queue if no conflict is determined and to update the register according to the pattern applied to the request, and resource enable logic that enables operations on the resource according to the register. An automatic wake-up mechanism may also be provided to keep the array active during extended periods of non-use.

Abstract: An integrated digital processing device and method for examining the operation thereof. An integrated multiple digital processing device has externally-accessible tag connections which provide signals representative of what circuit has access to external memory used by the processing device. The processing device includes a plurality of digital processor circuits, a DRAM refresh logic circuit, externally-accessible connections for receiving memory access signals from an external processor, and an arbitration circuit for determining which of the digital processor circuits, refresh logic circuit or external processor may have access to the external memory. The signals on the tag connections are provided by the arbitration circuit, and indicate which of the aforementioned circuits has access to the external memory at any moment.

Abstract: A number of remote I/O ICUs, enhanced PCI--PCI bridges, and an ICC bus interface unit are distributively provided to a computer system having a processor and an hierarchy of PCI buses for facilitating PCI agents coupled to the lower level PCI buses to interrupt the processor during operation. The remote I/O ICUs, the enhanced functions of the PCI--PCI bridges, and the ICC bus interface unit advantageously leverage the PCI--PCI bridges' conventional ability in handling PCI type 1 configuration write transactions, to facilitate interrupt delivery and end of interrupt notification, by employing two specially defined PCI type 1 configuration write transactions, one for interrupt messages and another for end-of-interrupt (EOI) messages.