Abstract: A method for manufacturing a substrate including a region, which is mechanically decoupled from a support and has at least one component situated on the region; at least one recess being introduced on a front side of the substrate; an etching pattern being prepared on a back side of the substrate and etched anisotropically in such a manner, that vertical channels are produced on the back side of the substrate; and subsequently, a cavity being introduced at the back side of the substrate; the at least one recess on the front side of the substrate being connected to the cavity on the back side of the substrate; and in at least one region between the front side of the substrate and the cavity, at least two recesses or at least two segments of a recess being interconnected by at least one channel.

Abstract: A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Abstract: An etching method is provided. In the etching method, a protective film-forming gas including an amine gas is supplied to a substrate having a surface on which a first film and a second film are formed, the first film and the second film having respective properties of being etched by an etching gas, and a protective film is formed to cover the first film such that the first film is selectively protected between the first film and the second film when the etching gas is supplied. Further, the second film is selectively etched by supplying the etching gas to the substrate after the protective film is formed.

Abstract: A manufacturing method of micro fluid actuator includes: providing a substrate; depositing a first protection layer on a first surface of the substrate; depositing an actuation region on the first protection layer; applying lithography dry etching to a portion of the first protection layer to produce at least one first protection layer flow channel; applying wet etching to a portion of a main structure of the substrate to produce a chamber body and a first polycrystalline silicon flow channel region, while a region of an oxidation layer middle section of the main structure is not etched; applying reactive-ion etching to a portion of a second surface of the substrate to produce at least one substrate silicon flow channel; and applying dry etching to a portion of a silicon dioxide layer to produce at least one silicon dioxide flow channel.

Abstract: The invention provides a method for polishing or planarizing a substrate of at least one of semiconductor, optical and magnetic substrates. The method includes attaching a polymer-polymer composite polishing pad having a polishing layer to a polishing device. A hydrophilic polymeric matrix forms the polishing layer. Cationic fluoropolymer particles having nitrogen-containing end groups are embedded in the polymeric matrix. A slurry containing anionic particles is applied to the polymer-polymer composite polishing pad and rubbed against the substrate to polish or planarize the substrate with the fluoropolymer particles interacting with the anionic particles to increase polishing removal rate.

Abstract: The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.

Abstract: The present invention relates to the unexpected discovery of novel methods of preparing nanodevices and/or microdevices with predetermined patterns. In one aspect, the methods of the invention allow for engineering structures and films with continuous thickness equal to or less than 50 nm.

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes a first silicon layer, a second silicon layer, and a first germanium-containing layer positioned between the first silicon layer and the second silicon layer. The method further includes selectively etching the first germanium-containing layer by exposing the film stack to a plasma that includes fluorine agents, nitrogen agents, and hydrogen agents. The plasma etches the first germanium-containing layer and causes a passivation layer to be formed on exposed surfaces of the first silicon layer and the second silicon layer to inhibit etching of the first silicon layer and the second silicon layer during exposure of the film stack to the plasma.

Abstract: A manufacturing method of an optical waveguide device that allows light to propagate through a core formed within a cladding formed on a substrate, the core having a higher refractive index than the cladding, includes: layering a first cladding-material layer for the cladding and a core-material layer for the core sequentially on the substrate; forming the layered core-material layer into the core having a waveguide shape, and removing a first part of the core, the first part being positioned at a portion where a slit is to be formed, to thereby form a gap in the core; layering a second cladding-material layer for the cladding to cover the first cladding-material layer and the core; and removing, by dry-etching, a second part of the first and second cladding-material layers, the second part being positioned at the portion where the slit is to be formed, to thereby form the slit.

Abstract: The disclosure relates to a method for manufacturing a planarized etch-stop layer, ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method includes providing a first planarized layer on top of a surface of a substrate, the first planarized layer having a patterned and structured metallic material and a filling material. The method further includes depositing on top of the first planarized layer the planarized ESL of an ESL material with low HF etch rate, wherein the planarized ESL has a low surface roughness and a thickness of less than 150 nm, in particular of less than 100 nm.

Abstract: Provided are wet etching compositions and methods for etching a surface of a microelectronic device that contains silicon nitride (SiN), silicon oxide, and polysilicon which in one embodiment is in contact with a surface comprising a compound which is electrochemically more noble than silicon, and optionally other materials which may include a conductive material, a semiconducting material, or an insulating material useful in a microelectronic device, or a processing material that is useful in preparing a microelectronic device.

Abstract: The present invention provides, in polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, means that is capable of improving a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials. The present invention relates to a polishing composition used for polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, the polishing composition containing: organic acid-immobilized silica; a dispersing medium; a selection ratio improver that improves a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials; and an acid, in which the selection ratio improver is organopolysiloxane having a hydrophilic group.

Abstract: Smoothness of glass is improved. A polishing slurry (A) contains amorphous carbon and water, and a total amount of the amorphous carbon and the water is equal to or more than 90% of the whole polishing slurry in terms of mass ratio.

Abstract: A non-phosphoric acid-based silicon nitride film etching composition includes 5 to 50 wt % of an organic acid-based chelating agent including an organic phosphonic acid group, a carboxylic acid group, or a combination thereof, based on a total weight of the etching composition. The etching composition for pressurization suppresses etching a silicon oxide film and selectively etches a silicon nitride film in a vertically laminated structure in which both the silicon nitride film and the silicon oxide film are exposed to a surface or the silicon nitride film and the silicon oxide film are alternately laminated.

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Abstract: A slurry for polishing surfaces or substrates that at least partially comprise ruthenium and copper, wherein the slurry includes an alkali hydroxide, oxygenated halogen compound, and a halogen alkyl benzotriazole. The slurry may further include abrasive, acid(s), and, optionally, an alkoxylated alcohol. With these components, the slurry exhibits a high ruthenium to copper removal rate ratio.

Abstract: A composition comprises, consists of, or consists essentially of a polymer including a derivatized amino acid monomer unit. A chemical mechanical polishing composition includes a water based liquid carrier, abrasive particles dispersed in the liquid carrier, and a cationic polymer having a derivatized amino acid monomer unit. A method of chemical mechanical polishing includes utilizing the chemical mechanical polishing composition to remove at least a portion of a metal or dielectric layer from a substrate and thereby polish the substrate.

Abstract: The present disclosure includes apparatuses and methods related to freezing a sacrificial material in forming a semiconductor. In an example, a method may include solidifying, via freezing, a sacrificial material in an opening of a structure, wherein the sacrificial material has a freezing point below a boiling point of a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to a particular temperature range.