Patents Examined by John A Lane
  • Patent number: 11966298
    Abstract: The present application provides a data backup method and a restoration method for an NVDIMM, an NVDIMM controller and an NVDIMM. The NVDIMM (200) comprises a DRAM (201), a NAND flash memory (202) and an NVDIMM controller (100), the NVDIMM controller (100) controlling the NVDIMM (200) and comprising a DDR controller (101), a NAND flash memory controller (102), a data backup module (103) and a data restoration module (104), the DDR controller (101) using and enabling DBI mechanism. During data backup, the DDR controller (101) reads N-bit DQi and 1-bit DBI from the DRAM (201) and sends the same to the data backup module (103). When DBIi is “1”, the data backup module (103) compares the DQi and DQi-1. If the number of bits of the DQi and the DQi-1 with different values is greater than N/2, then the DQi is inverted and the DBIi is set to “0”, and otherwise the DQi and the DBIi are remained unchanged. When the DBIi is “0”, the DQi and the DBIi are remained unchanged.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 23, 2024
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Xiaofeng Zhou, Xiping Jiang
  • Patent number: 11966635
    Abstract: A memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (LUNs) and are associated with corresponding LUN queue groups. Each LUN queue group may include LUN queues that are each associated with a respective intra-LUN priority level that indicates a priority of a LUN queue within a LUN queue group. The LUN queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a LUN queue across LUN queue groups. A quantity of intra-LUN priority levels may be greater than a quantity of execution priority levels. A LUN scheduler may be configured to select and transfer commands from LUN queue groups to the execution queue group based on intra-LUN priority levels. A command executor may be configured to execute commands from the execution queue group based on execution priority levels.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shakeel Isamohiuddin Bukhari, Mark Ish
  • Patent number: 11960747
    Abstract: A memory unit (23,24) is proposed for a computer system having a processing unit and a data bus for transferring data between the processing unit and the memory unit. The memory unit (23,24) stores data at a plurality of locations (“data items”) in a logical memory space (32), such that each data item has an address given by at least one index variable. In addition to read and write commands, the memory unit is operative to receive a shift command in a predefined format and including shift data which indicates a source address in the logical space. Upon receiving the command, the memory unit is operative to recognise it as a shift command and accordingly perform a predefined shift function comprising (i) using the source address to identify a portion of data in the memory space and (ii) writing that portion of data to a different location in the memory space. Thus, the portion of data can be shifted within the memory space without a need to transfer the portion of data along the bus.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 16, 2024
    Assignee: BLUESHIFT MEMORY LTD
    Inventor: Peter Marosan
  • Patent number: 11960749
    Abstract: A host of a storage system is coupled to multiple SSDs. Each SSD is configured with a migration cache, and each SSD corresponds to one piece of access information. The host obtains migration data information of to-be-migrated data in a source SSD, determines a target SSD, and sends a read instruction carrying information about to-be-migrated data and the target SSD to the source SSD. The source SSD reads a data block according to the read instruction from a flash memory of the source SSD into a migration cache of the target SSD. After a read instruction is completed by the SSD, the host sends a write instruction to the target SSD to instruct the target SSD to write the data block in the cache of the target SSD to a flash memory of the target SSD.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: April 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ge Du, Yu Hu, Jiancen Hou
  • Patent number: 11954336
    Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xing Wang, Liu Yang, Xiaolai Zhu, Bin Zhao
  • Patent number: 11947808
    Abstract: A computer-implemented method according to one aspect includes monitoring a current usage of a backup storage space for a storage volume; comparing the current usage to a capacity threshold; and conditionally increasing a size of the backup storage space, based on the comparing and a predetermined size limitation.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nedlaya Yazzie Francisco, Theresa Mary Brown, Nicolas Marc Clayton, David Fei, Terry O'Connor
  • Patent number: 11941297
    Abstract: Techniques are provided for implementing garbage collection and bin synchronization for a distributed storage architecture of worker nodes managing distributed storage composed of bins of blocks. As the distributed storage architecture scales out to accommodate more storage and worker nodes, garbage collection used to free unused blocks becomes unmanageable and slow. Accordingly garbage collection is improved by utilizing heuristics to dynamically speed up or down garbage collection and set sizes for subsets of a bin to process instead of the entire bin. This ensures that garbage collection does not use stale information about what blocks are in-use, and ensures garbage collection does not unduly impact client I/O processing or conversely falls behind on garbage collection. Garbage collection can be incorporated into a bin sync process to improve the efficiency of the bin sync process so that unused blocks are not needlessly copied by the bin sync process.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 26, 2024
    Assignee: NetApp, Inc.
    Inventors: Manan Dahyabhai Patel, Wei Sun
  • Patent number: 11936521
    Abstract: Techniques discussed herein relate to providing in-memory workflow management at an edge device (e.g., a computing device distinct from and operating remotely with respect to a data center). The edge device can operate as a computing node in a computing cluster of edge devices and implement a hosting environment (e.g., a distributed data plane). A work request can be obtained by an in-memory workflow manager of the edge device. The work request may include an intended state of a data plane resource (e.g., a computing cluster, a virtual machine, etc.). The in-memory workflow manager can determine the work request has not commenced and initialize an in-memory execution thread to execute orchestration tasks to configure a data plane of the computing cluster according to the intended state. Current state data corresponding to the configured data plane may be provided to the user device and eventually displayed.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: March 19, 2024
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Prachi Maheshwari, Igors Sajenko, David Dale Becker, Maxim Baturin
  • Patent number: 11934686
    Abstract: A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
  • Patent number: 11928344
    Abstract: A system and method provides an integrated buffer management with flow control, in some cases via credits that may be redeemed for buffers, and interprocess communication.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: March 12, 2024
    Assignee: Yellowbrick Data, Inc.
    Inventor: Mark Brinicombe
  • Patent number: 11914898
    Abstract: Various implementations described herein relate to creating a namespace in response to determining that a sum of namespace sizes of a plurality of namespaces is less than a first threshold for the point of thin-provisioning. A write command and data are received from a host. The write command and the data are received in response to determining that a sum of namespace utilization of the plurality of namespaces is less than a second threshold. The data is compressed and stored in the created namespace.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: February 27, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Steven Wells, Neil Buxton
  • Patent number: 11914494
    Abstract: A storage device read-disturb-based read temperature map utilization system includes a storage device chassis housing a storage subsystem. A local read temperature utilization subsystem in the storage device chassis determines read disturb information for a plurality of blocks in the storage subsystem, uses it to identify a subset of rows in block(s) in the storage subsystem that have a relatively higher read temperature and, based on those read temperature identifications, generates a local logical storage element read temperature map that identifies a subset of logical storage elements associated with the storage subsystem that have a relatively higher read temperature. The local read temperature utilization subsystem then moves data from first block(s) in the storage subsystem to second block(s) in the storage subsystem based on relative read temperatures identified in the local logical storage element read temperature map.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
  • Patent number: 11914884
    Abstract: Techniques are provided for storing immutable snapshot copes in write once read many (WORM) storage. A snapshot of a volume may be stored into one or more objects formatted according to an object format. An expiry time may be assigned to the snapshot and the one or more objects based upon a creation time of the snapshot and a retention time. The one or more objects may be stored within a remote object store. The one or more objects are retained in an immutable state and cannot be deleted until expiration of the expiry time. In response to identifying an existing object within the remote object store comprising shared snapshot data referenced by the snapshot, an assigned expiry time of the existing object may be modified based upon the expiry time of the snapshot to create a modified expiry time for the existing object.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 27, 2024
    Assignee: NetApp, Inc.
    Inventors: Atul Ramesh Pandit, Tijin George
  • Patent number: 11907547
    Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jonathan S. Parry, Xiaojiang Guo
  • Patent number: 11907556
    Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
  • Patent number: 11907553
    Abstract: In an embodiment, a storage device is provided. A device controller with a memory is coupled with the storage device. The memory stores an application with instructions that direct the controller to receive a storage device policy. The instructions further direct the controller to store content from a storage request in accordance with the storage device policy, and record storage information, including at least a content identifier, to the memory. Subsequent to storing the content, the instructions further direct the controller to retrieve the content according to the storage information received in a storage request. According to an implementation, the instructions further provide instruction to refuse a delete request in accordance with the storage information. According to an implementation, the instructions provide direction to store the storage information at a remote location.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Gaea LLC
    Inventors: Joshua Johnson, Curt Bruner, Jeffrey Reh, Christopher Squires, Brian Wilson
  • Patent number: 11899932
    Abstract: Embodiments of the present invention generally provide for multi-dimensional disk arrays and methods for managing same and can be used in video surveillance systems for the management of real-time video data, image data, or combinations thereof.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: February 13, 2024
    Assignee: NEC CORPORATION
    Inventors: Wing-Yee Au, Alan Rowe
  • Patent number: 11899777
    Abstract: Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 13, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Eric L. Pope
  • Patent number: 11892951
    Abstract: A key value (KV) store, a method thereof, and a storage system are provided herein. The KV store may include a key logger; and a processor configured to receive a first command for storing a first KV in the KV store, write a first value of the first KV to a first NAND page, generate an extent map for identifying the first memory page including the first value, write the extent map to a second memory page, append an entry for storing the first KV to the key logger, and update a device hashmap of the KV store to include a first key of the first KV, upon a threshold being met within the key logger.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: February 6, 2024
    Inventors: Kedar Shrikrishna Patwardhan, Nithya Ramakrishnan
  • Patent number: 11886708
    Abstract: Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Minjian Wu