Patents Examined by John Bodnar
  • Patent number: 11854822
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Patent number: 11855078
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11848391
    Abstract: An infrared detector and a method for manufacturing it are disclosed. The infrared detector contains an absorber layer responsive to infrared light, a barrier layer disposed on the absorber layer, a plurality of contact structures disposed on the barrier layer; and an oxide layer disposed above the barrier layer and between the plurality of the contact structures, wherein the oxide layer reduces the dark current in the infrared detector. The method disclosed teaches how to manufacture the infrared detector.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: December 19, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventor: Pierre-Yves Delaunay
  • Patent number: 11843001
    Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: December 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byounghak Hong, Seunghyun Song, Ki-Il Kim, Gunho Jo, Kang-Ill Seo
  • Patent number: 11837456
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Heidi M. Meyer, Ahmet Tura, Byron Ho, Subhash Joshi, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11837643
    Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien Hung Liu
  • Patent number: 11817352
    Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11805700
    Abstract: There is provided a laminated substrate having a piezoelectric film, including: a substrate; a first electrode film provided on the substrate; and a piezoelectric film provided on the first electrode film, wherein an oxide film containing an oxide represented by a composition formula of RuOx or IrOx, is provided on the piezoelectric film.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 31, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kenji Shibata, Kazutoshi Watanabe, Fumimasa Horikiri
  • Patent number: 11804547
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11791335
    Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Te Lin, Wei-Yuan Lu, Feng-Cheng Yang
  • Patent number: 11793083
    Abstract: An object of the present invention is to provide a vibration sensor in which the frequency dependence of the output is small. The present invention provides a vibration sensor 1 comprising: a support 2; an organic piezoelectric material 3 deformably disposed in or on the support 2; and an electrode 4 for extracting an electrical signal generated by deformation of the organic piezoelectric material 3, the electrode 4 being formed on the organic piezoelectric material 3, the organic piezoelectric material 3 comprising a copolymer of vinylidene fluoride and one or more monomers copolymerizable with vinylidene fluoride.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 17, 2023
    Assignees: DAIKIN INDUSTRIES, LTD., OSAKA UNIVERSITY
    Inventors: Shinya Bitou, Tetsuhiro Kodani, Saori Sakami, Takashi Kanemura, Tsuyoshi Sekitani, Takafumi Uemura, Shusuke Yoshimoto
  • Patent number: 11784213
    Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungmin Park, Hanjin Lim, Haeryong Kim, Younglim Park, Cheoljin Cho
  • Patent number: 11778829
    Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Changhan Kim, In Ku Kang, Sun Young Kim
  • Patent number: 11777046
    Abstract: An energy storage device comprising a substrate comprising a groove having a first and a second face. A capacitor material in the groove. The first and the second face of the groove having a coat of metal. Wherein the coat of metal on the first face is not in electrical contact with the coat of metal on the second face.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 3, 2023
    Assignee: POWER ROLL LIMITED
    Inventor: Alexander John Topping
  • Patent number: 11776896
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Yuan Chang, Chia-Ping Lai, Chien-Chang Lee
  • Patent number: 11767217
    Abstract: A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.
    Type: Grant
    Filed: January 23, 2022
    Date of Patent: September 26, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: Ranganathan Nagarajan, Jia Jie Xia, Rakesh Kumar, Bevita Kallupalathinkal Chandran
  • Patent number: 11765912
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • Patent number: 11758711
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-Hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Patent number: 11750981
    Abstract: Provided is a transducer that can be manufactured without using a volatile adhesive or an organic solvent. A transducer is provided with: a first electrode sheet provided with a plurality of first through-holes; a dielectric layer, of which a first surface is disposed on the first-electrode-sheet side; and a first fusion-bonding layer formed from a fusion-bonding material, the first fusion-bonding layer joining together, by fusion bonding of the fusion-bonding material, a boundary region between a body portion of the dielectric layer and a first inner surface of the first electrode sheet and a boundary region between the body portion of the dielectric layer and a first inner circumferential surface of at least some of the plurality of first through-holes.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 5, 2023
    Assignee: Sumitomo Riko Company Limited
    Inventors: Katsuhiko Nakano, Masaki Nasu, Koichi Hasegawa, Shinya Tahara
  • Patent number: 11742338
    Abstract: A display apparatus includes a driving substrate and a first light emitting diode element. The driving substrate has a plurality of driving structures. Each of the driving structures includes a first pad, a second pad, a third pad and a fourth pad. The plurality of driving structures include a first driving structure. The first light emitting diode element is electrically connected to a first pad and a second pad of the first driving structure, and the first light emitting diode element crosses a line connecting a third pad and a fourth pad of the first driving structure. A manufacturing method of the display apparatus is also provided.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: August 29, 2023
    Assignee: Au Optronics Corporation
    Inventor: Chung-Chan Liu