Patents Examined by John F. Niebling
  • Patent number: 6919273
    Abstract: A TiSiN film is used as a barrier metal layer for a semiconductor device to prevent the diffusion of Cu. The TiSiN film is formed by a plasma CVD process or a thermal CVD process. TiCl4 gas, a silicon hydride gas and NH3 gas are used as source gases for forming the TiSiN film by the thermal CVD process. TiCl4 gas, a silicon hydride gas, H2 gas and N2 gas are used as source gases for forming a TiSiN film by the plasma CVD process.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: July 19, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Hayashi Otsuki, Kunihiro Tada, Kimihiro Matsuse
  • Patent number: 6916727
    Abstract: A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: July 12, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Christopher W. Leitz, Minjoo L. Lee, Eugene A. Fitzgerald
  • Patent number: 6909154
    Abstract: Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of the top surface of a semiconductor device, annealing at least a portion of the device, and removing a substantial portion of the one or more sacrificial layers, where the removing results in no substantial physical alterations to the device.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 21, 2005
    Assignee: Intel Corporation
    Inventors: Mark Y. Liu, Justin K. Brask
  • Patent number: 6908784
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: June 21, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 6909111
    Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: June 21, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Yoshimi Adachi, Noriko Shibata
  • Patent number: 6906449
    Abstract: The present invention embodies a solid state thermionic energy converter and is directed to a method and apparatus for conversion of thermal energy to electrical energy, and electrical energy to refrigeration. The present invention maintains a thermal separation between an emitter and a collector through a fractional surface contact of decreasing cross-sectional area towards the point of contact. The fractional surface contacts may be associated with the emitter, a barrier, or the collector. Maintaining a thermal separation between the emitter and the collector provides for ballistic electron transport through the barrier and reduces the transport of electrons through thermal conductivity. Hence, the efficiency is increased through the collection of ballistic electrons and the reduction of thermal conductivity electrons which cannot be collected. The inventive principle works for hole conductivity, as well as for electrons.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: June 14, 2005
    Assignee: C.P. Baker Securities, Inc.
    Inventors: Yan R. Kucherov, Peter L. Hagelstein
  • Patent number: 6903446
    Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: June 7, 2005
    Assignee: Cree, Inc.
    Inventors: Ralph C. Tuttle, Christopher Sean Plunket, David B. Slater, Jr., Gerald H. Negley, Thomas P. Schneider
  • Patent number: 6900092
    Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Atul C. Ajmera, Dominic J. Schepis, Michael D. Steigerwalt
  • Patent number: 6900094
    Abstract: A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: May 31, 2005
    Assignee: AmberWave Systems Corporation
    Inventors: Richard Hammond, Matthew Currie
  • Patent number: 6900877
    Abstract: A method and apparatus is provided for determining substrate drift from its nominal or intended position. The apparatus includes at least two fixed reference points. The reference points can be fixed with respect to the processing tool, or with respect to the end effector. As a robotic arm moves the end effector and substrate along a path, a camera captures images of the edge of the substrate and the reference points. Two or more cameras can also be provided. A computer can then calculate positional drift of the substrate, relative to its expected or centered position on the end effector, based upon these readings, and this drift can be corrected in subsequent robotic arm movement.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: May 31, 2005
    Assignee: ASM American, Inc.
    Inventor: Ivo Raaijmakers
  • Patent number: 6897076
    Abstract: A lithography system includes a pre-process apparatus which performs a pre-process for a substrate and an exposure apparatus which exposes the substrate pre-processed by the pre-process apparatus to a pattern. The pre-process apparatus includes a first control unit which transmits an instruction for starting exposure preparation to the exposure apparatus, and the exposure apparatus includes a second control unit which causes exposure preparation to start in accordance with the instruction transmitted from the pre-process apparatus.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: May 24, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoshi Sugiura
  • Patent number: 6897075
    Abstract: A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 24, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher A. Bode, Alexander J. Pasadyn
  • Patent number: 6897105
    Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: May 24, 2005
    Assignee: Texas Instrument Incorporated
    Inventors: Glen D. Wilk, Robert M. Wallace, John M. Anthony, Paul McIntyre
  • Patent number: 6897422
    Abstract: A scanning electron microscope is integrated in a common measuring configuration with at least one device for the angle-dependent measuring of the scattering or diffraction of light. This measuring configuration includes a common transport system, which handles the distribution of semiconductor wafers that are to be measured. The measuring configuration also includes at least one loading and unloading station for providing semiconductor wafers in wafer transport containers. The joint configuration of the two-measuring devices for measuring the critical dimension of a feature allows a mostly contamination-free, rapid, and flexible exchange between the two measuring devices, and furthermore the measuring of lots can be planned in accordance with various measuring strategies. In particular, each semiconductor wafer of a lot can be measured without resorting to sampling strategies. Certainty is enhanced with respect to wafer-to-wafer uniformity, and a greater throughput is achieved.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: May 24, 2005
    Assignee: Infineon Technologies AG
    Inventor: Oliver Broermann
  • Patent number: 6896765
    Abstract: A method for processing a plurality of substrates in a plasma processing chamber of a plasma processing system, each of the substrate being disposed on a chuck and surrounded by an edge ring during the processing. The method includes processing a first substrate of the plurality of substrates in accordance to a given process recipe in the plasma processing chamber. The method further includes adjusting, thereafter, a capacitance value of a capacitance along a capacitive path between a plasma sheath in the plasma processing chamber and the chuck through the edge ring by a given value. The method additionally includes processing a second substrate of the plurality of substrates in accordance to the given process recipe in the plasma processing chamber after the adjusting, wherein the adjusting is performed without requiring a change in the edge ring.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: May 24, 2005
    Assignee: Lam Research Corporation
    Inventor: Robert J. Steger
  • Patent number: 6898065
    Abstract: A method and apparatus for a mixed-mode operation of an electrostatic chuck in a semiconductor substrate processing system. The chuck is operated in a voltage mode before and after a processing and is operated in a current mode during the processing to suppress arcing during the processing of a substrate.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: May 24, 2005
    Inventors: Brad Mays, Tetsuya Ishikawa, Sergio Fukuda Shoji
  • Patent number: 6897157
    Abstract: The present invention discloses a method of fabricating and repairing a mask without damage and an apparatus including a holder to mount a substrate; a stage to position the holder in a chamber; a pumping system to evacuate the chamber; an imaging system to locate an opaque defect in the substrate; a gas delivery system to dispense a reactant gas towards the defect; and an electron delivery system to direct electrons towards the opaque defect.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Ted Liang, Alan Stivers
  • Patent number: 6897919
    Abstract: A liquid-crystal display device is provided. The liquid-crystal display device comprises a first substrate having a pixel electrode, a signal line, a scanning line, and a driver driving one of the signal line and the scanning line, a second substrate opposing the first substrate and having a common electrode, a liquid-crystal layer formed between the pixel electrode and the common electrode, and a first shield placed opposite the driver so as to shield an electromagnetic wave radiated from the driver.
    Type: Grant
    Filed: August 11, 2001
    Date of Patent: May 24, 2005
    Assignee: Fujitsu Display Technologies Corporation
    Inventors: Hiromi Enomoto, Noriyuki Ohashi, Hong Yong Zhang
  • Patent number: 6897927
    Abstract: In a manufacturing method of a color liquid crystal display device, a first conductive film is formed on a transparent insulating substrate to form a gate electrode and a gate bus line (first PR process). A gate insulating film, a semiconductor layer, an ohmic layer, and a second conductive film are deposited to form an island of a thin film transistor and a drain bus line (second PR process). Then, color filters in respective three colors are formed in their respective predetermined regions on the transparent insulating substrate in succession (third through fifth PR processes). A black matrix is formed, and a drain electrode and a source electrode are formed in the island by removing the second conductive film and ohmic layer on a region corresponding to the channel region by using the black matrix as a mask (sixth PR process). Then, a planarization film and a pixel electrode are formed (seventh and eighth PR processes).
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: May 24, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Michiaki Sakamoto, Takahiko Watanabe, Yoshiaki Hashimoto, Syuusaku Kido
  • Patent number: 6893916
    Abstract: An integrated circuit structure for MOS-type devices including a silicon substrate of a first conductivity type; a first gate insulating regions selectively placed over the silicon substrate of the first conductivity tape; a first polycrystalline silicon layer selectively placed over the silicon substrate of the first conductivity type; a second gate insulating regions selectively placed over the first gate insulating regions and the first polycrystalline silicon layer; a second polycrystalline silicon layer selectively placed over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the first polycrystalline silicon layer and in contact therewith; and second buried silicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the second polycrystalline silicon layer and insulate
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: May 17, 2005
    Assignee: HRL Laboratories, LLC
    Inventors: James P. Baukus, Lap-Wai Chow, William M. Clark, Jr.