Patents Examined by John F. Niebling
  • Patent number: 6893948
    Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 17, 2005
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
  • Patent number: 6894782
    Abstract: There is provided a method of measuring defocusing when a semiconductor wafer is exposed to light. With the method, a resist is exposed to light by deviating a focus of the light by a given distance in relation to the semiconductor wafer with the resist applied thereto, and after development of the resist, resist patterns for measurement are formed. Based on respective lengths of the resist patterns for measurement, defocusing in relation to the resist is found.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: May 17, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Daigo Hoshino, Takahiro Yamauchi
  • Patent number: 6893882
    Abstract: A multiple run by run process is described. A plurality of tools and a plurality of products to be run on the tools are provided. Tool effects and product effects on a parameter are identified for each tool and each product. A desired recipe is calculated for each product on each tool based on the tool effects and product effects identified. Thereafter, the plurality of products is run on the plurality of tools. The desired recipe is updated after each run of each tool. Tool aging is calculated after each run of each tool based on the desired recipe used.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 17, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-I Sun, Ben Fung, Yi-Chuan Lo, Wei-Hsuang Huang, Hsiang-Min Lin
  • Patent number: 6892447
    Abstract: A method accurately calibrating a movement control system of mark recognition in a chip mounting device, comprising the steps of: recognizing a first recognition mark put on a head (2) and a second recognition mark (13) put on a stage (26) with two-field recognition means (7) so as to calibrate and update the preceding control parameters inputted into the movement control system of the two-field recognition means (7); and, with the head (2) lowered to position the first recognition mark closely to the second recognition mark (13), recognizing both marks with third recognition means (20) when the two-field recognition means (7) is moved back so as to calibrate and update the preceding control parameters inputted into the movement control system of the two-field recognition means (7).
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: May 17, 2005
    Assignee: Toray Engineering Company, Limited
    Inventors: Akira Yamauchi, Yoshiyuki Arai
  • Patent number: 6893987
    Abstract: An alignment pattern is required for photo masks to be exactly aligned with one another; an amorphous silicon is deposited over the entire surface of an insulating layer except for an area where the alignment pattern is to be formed, and a pattern for an ion-implantation and the alignment pattern are concurrently transferred to a photo resist layer; dopant impurity is ion implanted into the amorphous silicon layer by using the photo resist mask, and the insulating layer is selectively etched also by using the photo resist mask; this results in simplification of the process sequence.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: May 17, 2005
    Assignee: NEC Corporation
    Inventors: Kunihiro Shiota, Fujio Okumura
  • Patent number: 6890839
    Abstract: An object of the present invention is to provide a laser annealing method and apparatus capable of performing uniform beam emission. By means of the present invention, uniform beam application to a sample can be achieved because a linear cross-sectional configuration can be created in an optical system with a beam having a Gaussian distribution while areas of strong light intensity are avoided by rotating the beam from a laser light source at a prescribed angle by means of rotating means even when the beam pattern of the beam from the laser light source has a non-uniform intensity distribution.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: May 10, 2005
    Assignee: Ishikawajima-Harima Heavy Industries Co., Ltd.
    Inventors: Norihito Kawaguchi, Kenichiro Nishida, Mikito Ishii, Takehito Yagi, Miyuki Masaki, Atsushi Yoshinouchi, Koichiro Tanaka
  • Patent number: 6890867
    Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Don Carl Powell
  • Patent number: 6890824
    Abstract: After forming a gate electrode on a semiconductor substrate, ion implantation is performed on the semiconductor substrate by using the gate electrode as a mask to form low concentration impurity regions, and thereafter first sidewall insulating films are formed on the side surfaces of the gate electrode. Next, by using the gate electrode and the first sidewall insulating films as a mask, ion implantation is performed on the semiconductor substrate to form high concentration impurity regions, and thereafter second sidewall insulating films are formed on the side surfaces of the first sidewall insulating films. After that, by using each sidewall insulating film as a mask, metal silicide layers are selectively formed on each surface of the semiconductor substrate and the gate electrode.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takayuki Yamada, Isao Miyanaga
  • Patent number: 6890403
    Abstract: A process for controlling the temperature of a substrate in a plasma processing reactor chamber comprising flowing a cooling gas to a substrate at a flow pressure; and determining a temperature of the substrate. The difference between the temperature of the substrate and a desired temperature of the substrate is determined; and a pressure by which the flow pressure of the cooling gas is to be adjusted is determined. The flow pressure of the cooling gas to the substrate is adjusted in accordance with the determined pressure.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: May 10, 2005
    Assignee: Applied Materials Inc.
    Inventors: Jeff S. Cheung, Alexandros T. Demos
  • Patent number: 6890823
    Abstract: Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 10, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeong-chan Lee, Si-young Choi, Chul-sung Kim, Jong-ryeol Yoo, Deok-hyung Lee
  • Patent number: 6891233
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 10, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Patent number: 6890774
    Abstract: The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: May 10, 2005
    Assignee: Lam Research Corporation
    Inventors: Janet M. Flanner, James C. Vetter
  • Patent number: 6889014
    Abstract: An exposure system includes a wafer processing apparatus for performing a preparation-for-exposure process on a wafer before an exposure process is performed, an exposure apparatus for performing the exposure process on the wafer subjected to the preparation-for-exposure process performed by the wafer processing apparatus, wherein the exposure apparatus also performs a calibration process to correct an error caused by a time-varying environmental parameter and/or caused by the exposure apparatus itself, and a host computer connected to the wafer processing apparatus and the exposure apparatus via communication means. Depending on the time needed for the wafer processing apparatus to perform the preparation-for-exposure process, the host computer outputs a calibration execution command for performing the calibration process to the exposure apparatus. Thereby, the total time from the start of processing a lot to the end thereof is minimized and thus, the total throughput is improved.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: May 3, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shin Takano
  • Patent number: 6887764
    Abstract: In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a substrate, wherein the auxiliary layer and the masking layer are patterned to determine an edge separating an area of the oxide layer covered by these layers from an exposed area thereof. Afterwards, an oxidation is performed to generate an oxide ramp in the area of the edge. Then, the auxiliary layer is partly removed to generate a hollow space of predetermined length between the oxide layer and the masking layer. A gate electrode material is introduced into the hollow space for generating a gate electrode.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: May 3, 2005
    Assignee: Infineon Technologies AG
    Inventors: Christian Herzum, Karlheinz Mueller
  • Patent number: 6888180
    Abstract: This invention provides a hetero-junction bipolar transistor (HBT) in which both a base resistance and a base-collector parasitic capacitance are decreased. The HBT has a collector (C) 18, a base (B) 20 and an emitter (E) 26. The collector comprises an outer collector region and an inner collector region, a thickness of the outer collector region is greater than that of the inner region. The base comprises an intrinsic region and an extrinsic region on the outer collector region, while the intrinsic base disposed on the inner collector region. The emitter is disposed on both the intrinsic base and the extrinsic base, and has a band gap energy greater than that of the base.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: May 3, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenji Kotani, Hiroshi Yano
  • Patent number: 6887759
    Abstract: The invention concerns a method for forming, in a substrate (1) having a first type of conductivity, a MOS transistor, comprising the following steps: a) forming on the substrate an insulated gate (3); b) implanting a doping agent having a second type of conductivity; c) forming on the edges of the gate silicon nitride spacers; d) simultaneously oxidising the apparent surfaces of the substrate, the gate and the spacers; and e) drain and source implantation.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Fran├žois Guyader, Franck Arnaud
  • Patent number: 6887744
    Abstract: A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an interlayer insulating film which is a film stack with mutually different dielectric constants and which covers the gate electrode, a source region contact hole and a drain region contact hole which are formed on the interlayer insulating film, a pixel electrode connected to the source region through the source region contact hole, a first conductive film connected to the drain region through the drain region contact hole and formed of the same film as that of the pixel electrode, and a second conductive film connected to the drain region through the first conductive film.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: May 3, 2005
    Assignee: Fujitsu Display Technologies Corporation
    Inventor: Kazushige Hotta
  • Patent number: 6884737
    Abstract: A method for providing a precursor to a supercritical processing chamber is provided. The precursor in solid form is provided in an ampoule external to the supercritical processing chamber. A fluid is provided to the ampoule, where at least a portion of the gas enters the solid precursor causing a melting point of the precursor to be depressed and thereby causing the solid precursor to melt. The melted precursor is delivered to the supercritical process chamber.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: April 26, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Jason M. Blackburn, Jeremie Dalton
  • Patent number: 6884655
    Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: April 26, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takahiro Iljima, Akio Rokugawa, Noriyoshi Shimizu
  • Patent number: 6884699
    Abstract: A process for making a polycrystalline silicon film includes forming, on a glass substrate, an amorphous silicon film having a first region and a second region that contacts the first region, forming a first polycrystalline portion by irradiating the first region of the amorphous silicon film with laser light having a wavelength not less than 390 nm and not more than 640 nm and forming a second polycrystalline portion that contacts the first polycrystalline portion by irradiating the second region and the portion of the region of the first polycrystalline portion that contacts the second region of the amorphous silicon film with the laser light.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: April 26, 2005
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Seiko Epson Corporation
    Inventors: Tetsuya Ogawa, Hidetada Tokioka, Junichi Nishimae, Tatsuki Okamoto, Yukio Sato, Mitsuo Inoue, Mitsutoshi Miyasaka, Hiroaki Jiroku