Abstract: This specification describes an information retrieval system such as a videotext or teletext system in which data is stored in conventional tree format, and the user has the usual capability to move vertically through the tree structure, but also has a novel capability to browse horizontally therethrough. This capability is achieved by providing each page of information with a browse link page pointer. The browse feature can be operated on an automatic repeat basis at a selected repetition rate, yet such automatic operation suspended at any time. In addition the user can return to normal vertical search procedure whenever desired.

Abstract: Instructions of a loop are repeatedly prefetched with a branch history table (46) made to store a predicted branch direction of "go" to branch for a branch count instruction of the loop. The loop is left without renewing the predicted branch direction when a prediction evaluating circuit (66) finds that the predicted branch direction is incorrect. Alternatively, the predicted branch direction is temporarily renewed to "no go" to branch during penultimate execution of the branch count instruction before leave of the loop and then renewed back to "go" to branch during ultimate execution of the branch count instruction on leaving the loop. It is possible in either event to again enter the loop at once. Only when there is no data for a branch count instruction, the predicted branch direction must be stored in the branch history table together with a predicted branch destination address for an instruction which stands foremost in the loop.

Abstract: An apparatus for controlling data movement between a peripheral and a data processing system, comprises a memory for storing data, wherein the memory comprises a plurality of memory modules. Each memory module corresponds to an assigned area of a first memory map, the first memory map being duplicated into a plurality of mirrored memory maps. Each mirrored memory map corresponds to a predefined operation, a composite of the first memory map and the plurality of mirrored memory maps forming a total memory space. Each memory location within the total memory space is defined by a unique memory space address. A processor performs a pseudo operation in response to a first control signal from the peripheral indicating data is available for being moved. A logic circuit generates at least one control signal in response to the pseudo operation such that a predetermined data movement operation occurs.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.

Abstract: A method and apparatus for efficient branching within a central processing unit with overlapped fetch and execute cycles which optimizes the efficient fetching of instructions.

Abstract: An information processing unit including a first and second memory, a numerical data generating circuit, and a logical data generating circuit. The first memory stores a plurality of instruction words and data. The second memory temporarily stores one of the instruction words read from the first memory. When this instruction word, temporarily stored in the second memory, is a first specific instruction word and a first field contained in that instruction word indicates generation of data, the numerical data generating circuit responds. When the instruction word stored in the second memory is a first or a second specific instruction word and a second field contained in that instruction word indicates generation of data, the logical data generating circuit responds.

Abstract: A transactional data base processing apparatus which executes plural transactions causing a data base to be updated, incorporates an after-image recovery storage apparatus and method which enables continuous operation of the transaction system. The after-image recovery storage apparatus has a temporary storage file and a permanent storage file with circuitry for writing from the temporary storage file to the permanent storage file. Tha circuitry also writes after-image updating data records to the temporary storage file. The apparatus further includes elements for initiating transfer of the after-image data records from the temporary storage file to the permanent storage prior to a time when the temporary file is filled with the data records. The transfer is accomplished by operating the apparatus on a time shared basis so that other ongoing operations including transactional operations occur as the after-image data is being transferred to a permanent storage device.

Abstract: A cash register system has a memory for storing the present time data counted by a time counting circuit and the present date data, and a memory for storing date changing data indicating a changing range of a data changing time with respect to a date renewal time on a calender day. When all the sales data are read out from a total memory and calculated in a total manner, the present time data and the date changing data, which are read out from the said memory means by a CPU, are compared with each other. When the former is not within the latter, the present time data is output as the date data of total calculation data. On the other hand, when the former is within the latter, the present date data is modified to have another date data, and the latter data is output as the date data for total calculation data.

Abstract: An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.

Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.

Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.

Abstract: A pattern matching apparatus wherein an input pattern is compared against a reference pattern by a distance or similarity measure (d.sub.ij) between data at respective time points (i, j) of the two patterns. An integration variable (g.sub.ij) of the distance measure is developed along a time path between the time axes of the two patterns to provide a measure of pattern matching. According to the invention, the path may deviate from 45.degree., i.e. the input pattern becomes locally time-compressed or time-expanded, only toward the time axis of the longer pattern. Therefore, local time compression or expansion is allowed only if the total input pattern length requires time compression or expansion, respectively, to match the total length of the reference pattern.

Abstract: A system for replacing the newspaper. A radio transmitter transmits the news as "pages" of code. The transmission is received in the home and the encoded pages stored in computer memory. The user selects pages from this memory for viewing on a monitor. That which is new is the storage of the entire news of a moment in mass memory in the home, permitting the user to select directly from this memory the material which he desires to read.

Abstract: A memory system in which a plurality of memory blocks are interleaved includes a temporary storage buffer, for example, a first-in, first-out buffer, for temporarily storing the data read out from the memory blocks.

Abstract: A computer system has a plurality of processors sharing a bus. Bus arbitration circuitry is located on each processor for determining bus access. The identity of the processor which is responsible for arbitrating bus access changes from time to time. Each processor has a plurality of possible arbitration states, which are controllable through execution of software by the processor.

Abstract: A table driven translator is provided which is capable of translating an input language into a machine-oriented language and handing changes in the syntax of the language inputted to a computer by rewriting a translation rule table.

Abstract: In the disclosed portable computer, a keyboard with keys for entering at least a full alphabet and ten digits is coupled to a computer system that includes a central processing unit which is in turn coupled to a display arrangement with a liquid crystal display. The entire computer is mounted in a case composed of a base and a cover hinged to the base. The base houses the computer system and the keyboard, and exposes the keyboard for operation by a user when the cover is open, while the cover houses the display arrangement and exposes the liquid crystal display on its inner surface. The cover is hinged at the edge of the base and, when closed, covers substantially the entire upper surface of the base.

Abstract: In order to prevent the unauthorized copying of software, a software module is encrypted using the data encryption standard (DES) algorithm, and the key is encrypted using the public key of a public/private key algorithm. To use the module it is entered into a software protection device where the private key held in a RAM 11 is used by a processor 13 to decode the DES key using instructions held in a ROM 12. Further instructions held by this ROM are used by the processor 13 to decode the module. Once the process of decoding keys and software has started, the processor 13 runs through a sequence of predetermined instructions and cannot be interrupted (except by switching off). When the sequence is complete processor 13, or for example a host computer 30, is enabled to use the decoded software, but a switch/reset circuit 17 operates preventing access to the RAM 11 and the ROM 12 so preserving the secrecy of the private key and any decoded DES key which is now stored in the RAM 11.

Abstract: Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the disk drive. The apparatus corresponding to each controller consists of suspended reserve logic and a register for retaining state indicating whether the controller has reserved the bus and state indicating whether the reserve operation has been suspended for the controller. The suspended reserve logic for a given controller receives inputs from the controller's bus, from the state stored in its register, and from the state in the suspended reserve apparatus for the other controller indicating whether that controller has reserved the disk drive. Outputs from the suspended reserve logic go to its register.