Abstract: A method and apparatus for depositing a low dielectric constant film includes depositing a silicon oxide based film, preferably by reaction of an organosilicon compound and an oxidizing gas at a low RF power level from about 10 W to about 500 W, exposing the silicon oxide based film to water or a hydrophobic-imparting surfactant such as hexamethyldisilazane, and curing the silicon oxide based film at an elevated temperature. Dissociation of the oxidizing gas can be increased in a separate microwave chamber to assist in controlling the carbon content of the deposited film. The moisture resistance of the silicon oxide based films is enhanced.

Abstract: A method for dynamically maintaining compatible contamination levels of equipment, wafer Lots and FOUP's used for automated processing of a Split Lot of wafers. Processing of the test Lot and the production Lot continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold and its designated contamination level is saved until the alternate processing or test Lot processing is completed. The contamination level of the Split Lot is reevaluated based on the completed process(es) and will be designated at the same level it carried at the Split or a higher contamination level if appropriate. The two Lots are then merged and given the highest contamination level of either the saved level or the Split Lot. The two Lots are then processed according to the original predefined process steps and at the redefined contamination level.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method for manufacturing a DRAM includes the steps of forming a gate oxide film, a polysilicon film and a tungsten silicide film consecutively on a silicon substrate, selective etching the tungsten silicide film, covering exposed side surfaces of the tungsten silicide film by a polysilicon side-wall film, selectively etching the polysilicon film, oxidizing the polysilicon side-wall film and exposed surfaces of the polysilicon film, and forming a gate electrode including the polysilicon film and the tungsten silicide film. The resultant DRAM has lower leakage current and excellent refresh characteristics due to less contamination of diffused regions by the tungsten particles.

Abstract: A method of fabricating a fluid-ejecting chip for an inkjet printer includes the step of forming CMOS layers on a wafer substrate. Nozzle chambers with ink ejection ports are formed on the wafer substrate. A sacrificial material is deposited on the wafer substrate. A shape memory material is deposited on the sacrificial material at a temperature above a transition temperature of the shape memory material with the shape memory material in a post-actuation shape. Heating circuits are formed on the sacrificial material to be in electrical contact with the CMOS layers and to heat the shape memory material upon receipt of an electrical signal from the CMOS layers to a temperature above the transition temperature. A stressed material is deposited on the sacrificial material. The sacrificial material is removed so that the shape memory material and the stressed material define a plurality of actuators that are operatively arranged with respect to the nozzle chambers.

Abstract: Process exhaust gas is sampled, and the components of the process exhaust gas are analyzed by a Fourier-transform infrared spectroscope (FT-IR) (26). The analysis result is compared with a reference analysis result obtained from an analysis of process exhaust gas generated in an operation performed under reference process conditions. If the amount of a gas component changes to an amount that is outside a predetermined range set around a reference value obtained from the reference analysis result, a signal indicating a process error is outputted. Instead of the output of the signal indicating a process error, the process conditions can be automatically adjusted.

Abstract: A method of preventing contaminating particles in a chamber in a deposition device is presented. In the method, a substrate is mounted within a chamber of gas-exposure equipment. The pressure within the chamber is reduced and a treatment gas is injected into the chamber to convert a surface of the substrate to be organic. After a desired time is elapsed, the pressure within the chamber is allowed increase to atmospheric pressure or above by introducing nitrogen gas into the chamber. Nitrogen gas introduction prevents entry of air, including the moisture within the air. Without the moisture, contaminating particles are not generated since the moisture is prevented from reacting with an ammonia component of the treatment gas.

Abstract: A fabrication process and a structure of a laminated capacitor. A substrate is provided, and multiple electrode and dielectric layers, formed using high-speed physical metal deposition and dielectric material coating, respectively, are alternately stacked to form a laminated capacitor structure. In addition, a pair of terminal electrodes is formed on two sides of the electrode layers. The terminal electrodes are electrically connected to the electrode layers. A surface metallic layer is formed on the exposed surface of the terminal electrodes to prevent the surface from being oxidized. Thereby, the adhesion between the electrode layers and the dielectric layers is improved. The thickness uniformity ratio of the dielectric layers can be maintained at about ∈±10%. The relative displacement between two neighboring electrode layers can be smaller than about 100 microns to approach the standard capacitance required by the laminated capacitor.

Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Abstract: The present invention provides methods of forming fuse box guard rings for integrated circuits and integrated circuit devices having the same. A fuse line is formed at a fuse portion of an integrated circuit device and a first insulating layer is formed on the fuse line. A guard ring pattern that encloses the fuse line is formed on the first insulating layer. A second insulating layer is formed on the guard ring pattern and the first insulating layer. The second insulating layer is partially etched to remove a portion of the second insulting layer in the fuse portion of the integrated circuit device enclosed by the guard ring pattern exposing a portion of the first insulating layer and to form a via hole in a peripheral circuit region of the integrated circuit device.

Abstract: A testing processor executes a plurality of test steps of an assembly test on successive units. A server informs the testing processor of a sampling frequency for each test step. The testing processor only executes those test steps whose sampling frequencies indicate that they are to be run on a particular unit. Upon detecting a failure associated with a particular test step, the server may inform the testing processor to adjust the sampling frequency of the particular test step such that the particular test step is to be executed on every subsequent unit to be tested. Upon receiving no further failures associated with the particular test step for a given number of units, the server may notify the testing processor to adjust the sampling frequency of the particular test step such that it need not be executed for every subsequent unit to be tested.

Abstract: A method for manufacturing a semiconductor device having a movable unit includes a step of forming an SOI substrate that includes a semiconductor substrate, an insulating layer, and a semiconductor layer. The method further includes a step of dry etching the semiconductor layer to form a trench and a step of dry etching a sidewall defining the trench at a portion adjacent to a bottom of the trench to form the movable unit. The later dry etching is implemented with a charge building up on a surface of the insulating layer that is exposed during the former dry etching to etch the portion. In addition, the later dry etching is implemented at an etching rate higher than that at which the former dry etching is implemented to reduce the deposition amount of a protection film deposited on a reverse side of the movable unit during the later dry etching.

Abstract: A dispatching method of manufacturing integrated circuit (IC) by push and pull two-way is to decide the dispatching orders of lots of wafers in each workstation. First, the priorities of lots of wafers is determined, and then the dispatching method of manufacturing IC by push and pull two-way is proceeded to run several push steps and pull steps. The push step is to dispatch wafers directly from upper process, no matter the lower units are crowded or delayed. On the other hand, the pull step is first to concern deficiencies in the lower unit, and then to dispatch wafers from the upper units. After proceeding the push steps and the pull steps, the other lots of wafers are dispatched by their original priorities. The dispatching method of manufacturing IC by push and pull two-way has the advantage of increasing the utilities of equipments.

Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.

Abstract: The transfer apparatus includes a light source, a transmission type image display device in which a liquid crystal layer is held between two sets of substrates and polarizing plates and a photosensitive recording medium. The light source, the image display device and the photosensitive recording medium are arranged in series along a direction in which light from the light source advances and the image display device and the photosensitive recording medium are arranged in a non-contact state. A display image transmitted from the transmission type image display device is transferred to the photosensitive recording medium. A distance between the image display device and the photosensitive recording medium and a sum total of thicknesses of the substrate and the polarizing plate at least on a side of the photosensitive recording medium in the image display device are set in accordance with a definition of the display image.

Abstract: Even though a conventional color LCD device further includes an extra element such as a color filter for color display, the present invention does not need the extra element. The liquid crystal layer is initially aligned parallel to the substrates and then re-aligned by the applied voltage. Transmittance for the specific wavelength is changed according to an angle between the transmission axis of the liquid crystal layer and the light axis of the polarizer. Thus, multiple colors or full color can be realized without the extra element for color display. Therefore, the transmittance of the LCD device is improved and the cost for the LCD device is reduced.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in a trench on a semiconductor substrate. In one embodiment, a method for forming a bottom oxide layer in a trench on a semiconductor substrate comprises depositing an oxide layer along the surface of the sidewall and the bottom of a trench on a semiconductor substrate which has top layers, depositing a nitride layer along the surface of the said oxide layer, and forming a photo-resist filler in a trench. The top surface of the photo-resist filler is lower than the top surface of the substrate to expose a portion of the nitride layer uncovered by the photo-resist filler. The exposed portion of the nitride layer is removed to expose the oxide layer underneath. A portion of the oxide layer on the sidewalls of a trench is removed to form a bottom oxide layer in a trench.

Abstract: A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.