Abstract: A heating circuit is provided. The heating circuit is disposed in a chip which has a normal operation temperature range. The heating circuit includes a comparison circuit and a thermal-energy generation circuit. The comparison circuit compares a temperature voltage with a first threshold voltage. The temperature voltage represents a temperature of the chip. The thermal-energy generation circuit is controlled by the comparison circuit. When the temperature voltage is less than the first threshold voltage, the comparison circuit enables the thermal-energy generation circuit to generate thermal energy to raise the temperature of the chip.

Abstract: An electronic apparatus includes: an electronic module; a display panel disposed on the electronic module and including a first display region and a second display region adjacent to the first display region, the second display region overlapping the electronic module; and a polarization plate disposed on the display panel and including a first polarization region overlapping the first display region and a second polarization region including a polarization part and a non-polarization part having higher light transmittance than the polarization part, the non-polarization part overlapping the second display region.

Abstract: A program editing device edits a machining program in which a machining path along which a wire electrode of a wire electrical discharge machine machines a workpiece is defined. The machining program includes a plurality of blocks corresponding to respective multiple partial paths into which the machining path is divided, each of the blocks including path information indicating the corresponding partial path. The program editing device includes an analyzer analyzing the machining program and thereby identifying a predetermined shape pattern formed by a series of the multiple partial paths in the machining path, an information generator generating shape information corresponding to the identified predetermined shape pattern, and an editor inserting the shape information into the machining program.

Abstract: The invention discloses a method for preparing an anticorrosive surface layer of a metal material in a marine environment by laser, which belongs to the technical field of laser processing. First, the laser cladding method is used to prepare a cladding surface layer on the surface of the metal material that is not easy to undergo chemical substitution reaction with the chlorides (NaCl, MgCl2 , CaCl2 etc.) in the seawater. Then, on the surface of the cladding surface layer, ultrafast laser processing is used to form a surface layer with a wetting angle (and water) greater than 90 degrees and with hydrophobic characteristics.

Abstract: In a first aspect, the present disclosure relates to a method for forming a patterning mask over a layer to be patterned, the method comprising: (a) providing a first layer over a substrate, the substrate comprising the layer to be patterned, the first layer being capable to bond with a monolayer comprising a compound comprising a functional group for bonding to the first layer and a removable organic group, (b) bonding the monolayer to the first layer, (c) exposing the monolayer to an energy beam, thereby forming a pattern comprising a first area comprising the compound with the removable organic group and a second area comprising the compound not having the removable organic group, and (d) selectively depositing an amorphous carbon layer on top of the first area.

Abstract: This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

Abstract: In certain examples, methods and semiconductor structures are directed to multilayered structures including TMD (transition metal dichalcogenide material or TMD-like material and a polymer-based layer which is characterized as exhibiting flexibility. A first layer including a TMD-based material (e.g., an atomic-thick layer including TMD) or TMD-like material is provided or grown on a surface which in certain instances may be a rigid platform or substrate. A plurality of electrodes are provided on or as part of the first layer, and another layer or film including polymer is applied to cover the first layer and the electrodes. The other layer is integrated with the TMD material or TMD-like material and the first layer, and the other layer provides a flexible substrate such as when released from the exemplary rigid platform or substrate.

Abstract: The present disclosure relates to the technical field of production of H-shaped steel and discloses a production line of H-shaped steel and a production method. By arrangement of the assembly zone in which a welding line is arranged and the welding zone in which a welding line is arranged, a process layout of assembly and welding flow type machining production line can be formed. Assembly and welding of a stiffening plate are operated independently, and a carrying robot, a spot welding robot and a welding robot are movable between stations. A transfer device transfers an H-shaped workpiece in the process of feeding, machining and discharging, thereby implementing flow type machining, which can effectively improve machining efficiency. Through the production method, the assembly and welding flow type machining of the stiffening plate can be implemented, thereby effectively improving machining efficiency.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Abstract: Provided is a semiconductor device. The semiconductor device includes a wafer; an etch stop layer on the wafer; a lower mold layer on the etch stop layer; an intermediate supporter layer on the lower mold layer; an upper mold layer on the intermediate supporter layer; an upper supporter layer on the upper mold layer; and a hard mask structure on the upper supporter layer, wherein the hard mask structure includes a first hard mask layer on the upper supporter layer and a second hard mask layer on the first hard mask layer, one of the first hard mask layer and the second hard mask layer includes a first organic layer including a SOH containing C, H, O, and N, and the other one of the first hard mask layer and the second hard mask layer includes a second organic layer including an SOH containing C, H, and O.

Abstract: A semiconductor device includes a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the via includes a contact to at least one of the transistors.

Abstract: An adjustment of the amount of energy in at least one specific applying unit is executed when energy is applied to a cylindrical member pair in which another cylindrical member is inserted inside a cylindrical member to melt and weld the cylindrical member pair in a circumferential direction. The adjustment is executed in association with a rotation angle to satisfy a relationship of Pd+Pw>?, wherein Pd is an output decease rotation angle that decreases the energy amount from a steady energy amount HP applied from the specific applying unit in a welding end process, Pw is an overlap rotation angle at which the irradiation parts around the cylindrical member pair overlap with the steady energy amount HP, and ? is a separation angle between the specific applying unit and another applying unit adjacent to each other in a rotation direction around the axis.

Abstract: The invention relates to a photoplethysmography (PPG) sensing device comprising—a pulsed light source, —at least one pixel to create photo-generated electrons, synchronized with said pulsed light source. It is mainly characterized in that each pixel comprises: —a pinned photodiode (PPD) having two electronic connection nodes, —a sense node (SN), to convert the photo-generated electrons into a voltage, and—a Transfer Gate (TGtransfer) transistor, having its source electronically connected to one electronic connection node of said pinned photodiode (PPD), and being configured to act as a transfer gate (TG) between said pinned photodiode (PPD) and said sense node (SN), allowing the photo-generated electrons to sink when the light is pulsed-off, the photo-generated electrons integration when the light is pulsed-on and the transfer of at least part of the integrated photo-generated electrons to said sense node for a read-out.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a system for processing a substrate includes a process chamber comprising a first processing volume and a second processing volume, a carrier disposed in the first processing volume, comprising a first thermoelectric module (TEM), and configured to support the substrate while the substrate is being heated or cooled, a chuck disposed within the second processing volume, comprising a second TEM, and configured to receive the substrate from the carrier and to support the substrate while the substrate is being heated or cooled, and a system controller configured to monitor a temperature of at least one of the substrate, the carrier, or the chuck during operation, and based on the temperature of the at least one of the substrate, the carrier, or the chuck, supply current to at least one of the first TEM or the second TEM.

Abstract: Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes the following operations. A substrate is provided, includes a core region and a peripheral region. A preset barrier layer is formed on the substrate, and covers the core region and the peripheral region. At least a part of the preset barrier layer corresponding to the peripheral region is removed to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer. A dielectric layer and a first conductive layer are successively formed on the first barrier layer and the substrate. A part of the dielectric layer and the first conductive layer on the first barrier layer are removed, to reserve a part of the dielectric layer and the first conductive layer on the first barrier layer closer to the peripheral region.

Abstract: A substrate processing apparatus includes: a rotary stage configured to hold a substrate; a rotary driver configured to rotate the rotary stage around a rotation axis; at least one electric heater installed in the rotary stage; at least one power receiving coil installed in the rotary stage and electrically connected to the electric heater; at least one power feeding coil installed to face the power receiving coil in a direction of the rotation axis with a gap between the power feeding coil and the power receiving coil; and a radio-frequency power supply unit configured to supply radio-frequency power to the power feeding coil.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.