Patents Examined by John P Dulka
  • Patent number: 11329141
    Abstract: Semiconductor device structures comprising a spacer feature having multiple spacer layers are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region, and a contact etching stop layer on the spacer feature.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 11327227
    Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: October 3, 2021
    Date of Patent: May 10, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11328950
    Abstract: Embodiments of the disclosure relate to a method for fabricating semiconductor-on-insulator (SemOI) electronic components. In the method, a device wafer is bonded to a handling wafer. The device wafer includes a semiconductor device layer and a buried oxide layer. A substrate is adhered to the handling wafer. The substrate is a glass or a ceramic, and bonding occurs at an interface between the semiconductor device layer and the substrate. Material is removed from the device wafer to expose the buried oxide layer. The substrate is debonded from the handling wafer so as to provide an SemOI electronic component including the substrate, the semiconductor device layer, and the buried oxide layer.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: May 10, 2022
    Assignee: Corning Incorporated
    Inventors: Ya-Huei Chang, Jen-Chieh Lin, Jian-Zhi Jay Zhang
  • Patent number: 11322528
    Abstract: The present disclosure provides a manufacturing method of a TFT pattern, and a mask, which is used to make light pass through a hole corresponding to a position of the TFTs on the mask which is disposed on the TFTs, thereby producing two or more stacked photoresists on the TFTs to counteract a reflected light on a semiconductor As layer and ensure normal working of the TFTs.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 3, 2022
    Inventors: Shuting Zhong, Ning Zhang
  • Patent number: 11322442
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 3, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshimitsu Obonai, Masami Jintyou, Daisuke Kurosaki
  • Patent number: 11322407
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: May 3, 2022
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11315911
    Abstract: A combined display panel including a first sub-screen and a second sub-screen. The first sub-screen includes a first display surface and a second display surface disposed on a back of the first display surface, the first display surface includes a plurality of first sub-pixels, the second display surface includes a plurality of second sub-pixels, and the second sub-screen includes a plurality of third sub-pixels. The combined display panel provided by the present application can improve the aperture ratio of the display panel in the prior art.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 26, 2022
    Inventor: Baixiang Han
  • Patent number: 11307499
    Abstract: Embodiments of the present disclosure provide a splicing nano-imprint template, a repair method of a splicing seam thereof, and a manufacturing method thereof. The repair method of the splicing seam of the splicing nano-imprint template includes: providing a splicing nano-imprint plate, in which the splicing nano-imprint plate includes a base substrate and splicing modules that are positioned on the base substrate, a splicing seam is provided between adjacent spicing modules, and each of the splicing modules includes a unit pattern; forming a repair adhesive layer at least at the splicing seam; and performing a patterning process on the repair adhesive layer to form a repair module, in which the repair module includes the unit pattern.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 19, 2022
    Inventors: Yanhui Lu, Duohui Li, Xueyuan Zhou
  • Patent number: 11289322
    Abstract: A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 29, 2022
    Inventor: Fumimasa Hirikiri
  • Patent number: 11257908
    Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsi Yang, Ming-Hua Yu, Jeng-Wei Yu
  • Patent number: 11257765
    Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 22, 2022
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Kerui Xi, Feng Qin, Jine Liu, Xiaohe Li, Tingting Cui, Yuan Ding
  • Patent number: 11247296
    Abstract: A substrate-cutting stage includes a main stage and a dummy stage spaced apart from each other with a cutting region interposed therebetween and that support a substrate. The main stage supports a first portion of the substrate, the dummy stage supports a second portion of the substrate, and the cutting region overlaps a to-be-cut portion of the substrate disposed between the first and second portions.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: February 15, 2022
    Inventors: Eunju Kim, Seoin Han
  • Patent number: 11239222
    Abstract: Provided is a cooled optical transmission module device including a silicon wafer having a plurality of platform mounting grooves, each of which serves as a space for mounting in which an optical transmission platform therein, a thermoelectric cooler bonded to the platform mounting groove to transfer heat to outside, the optical transmission platform provided on the thermoelectric cooler and configured to output an optical signal by generating and reflecting the optical signal, a dielectric sub-mount bonded to the platform mounting groove of the silicon wafer and electrically connected to the mounted optical transmission platform, and a cover configured to cover the platform mounting groove of the silicon wafer and seal the platform mounting groove while providing an electric path.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 1, 2022
    Inventors: Eun Kyu Kang, Jong Jin Lee, Sang Jin Kwon, Won Bae Kwon, Dae Seon Kim, Soo Yong Jung
  • Patent number: 11233079
    Abstract: A camera module and a molded circuit board assembly thereof, a semi-finished product of the molded circuit board assembly, and an array camera module and a molded circuit board assembly thereof, as well as a manufacturing method and an electronic device, wherein the camera module comprises at least one optical lens, at least one back surface molded portion, at least one photosensitive element and a circuit board.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: January 25, 2022
    Inventors: Mingzhu Wang, Nan Guo, Zhenyu Chen, Takehiko Tanaka, Jingfei He, Zhen Huang, Zhongyu Luan, Feifan Chen
  • Patent number: 11232983
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: January 25, 2022
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 11227885
    Abstract: An image sensor package includes a substrate, a sensor chip, a light-permeable cover, and a particle blocking dam. The substrate has a chip accommodating space, and the sensor chip is disposed in the chip accommodating space and electrically connected to the substrate. The light-permeable cover is disposed on the substrate and disposed above the sensor chip. The particle blocking dam is disposed above the sensor chip and extends from the light-permeable cover toward the sensor chip so as to be in contact with or close to the sensor chip.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Inventors: Li-Chun Hung, Chien-Chen Lee
  • Patent number: 11227886
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate and a filter partially surrounded by the dielectric layer. The filter has a protruding portion protruding from a bottom surface of the dielectric layer. The image sensor device further includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the protruding portion of the filter. In addition, the image sensor device includes a reflective element between the shielding layer and an edge of the light sensing region.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volume Chien, Yun-Wei Cheng, Shiu-Ko Jangjian, Zhe-Ju Liu, Kuo-Cheng Lee, Chi-Cherng Jeng
  • Patent number: 11215921
    Abstract: A fabrication method comprises selecting an initial drop pattern defining a position of drops of a formable material, the initial drop pattern comprising a grid pattern of drops, designating the drops of the grid pattern to be dispensed by a first series of nozzles of a dispenser based on a spacing between drops in the Y-dimension; generating a modified drop pattern by shifting the grid pattern in a first direction along the Y-dimension, wherein a shift distance is selected such that the drops of the shifted grid pattern are designated to be dispensed from a second series of nozzles of the dispenser; dispensing the plurality of drops according to the modified drop pattern onto a substrate; during the dispensing of the drops, shifting a position of the stage or dispenser along the Y-dimension opposite to the first direction by an amount equal to the shift distance.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 4, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ecron D. Thompson, Craig William Cone, Logan L. Simpson, Wei Zhang, James W. Irving
  • Patent number: 11211487
    Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Haitao Liu
  • Patent number: 11211272
    Abstract: A method of contaminant detection comprises exposing a wafer comprising one or more contaminants to microdroplets of an oxidizer to form an oxide on a surface of the wafer, exposing the oxide to an etchant to remove the oxide and leave the one or more contaminants on the surface of the wafer, and determining a composition of the one or more contaminants. Additional methods and related tools are also disclosed.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Palsulich, Nicholas A. Wieber