Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.

Abstract: A method and apparatus for selectively replacing damaged portions of a data stream. The method comprises analyzing the data stream to identify damaged portions therein; selecting a damaged portion for replacement; and replacing the selected damaged portion. The selected damaged portion is selected for replacement in dependence on a rate of replacement, the rate of replacement being that at which previous portions of the data stream have been replaced.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

Abstract: A method begins by a processing module identifying a memory device having an expired useable memory life with respect to a legacy storage protocol. The method continues with the processing module extracting data from the memory device. The method continues with the processing module reprovisioning the memory device from the legacy storage protocol to a dispersed storage error coding storage protocol.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.

Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Abstract: Systems and methods are disclosed for remapping codewords for storage in a non-volatile memory, such as flash memory. In some embodiments, a controller that manages the non-volatile memory may prepare codeword using a suitable error correcting code. The controller can store a first portion of the codeword in a lower page of the non-volatile memory may store a second portion of the codeword in an upper page of the non-volatile memory. Because upper and lower pages may have different resiliencies to error-causing phenomena, remapping codewords in this manner may even out the bit error rates of the codewords (which would otherwise have a more bimodal distribution).

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to encode or decode a packet based on a base parity check matrix and a set of lifting values. In a particular embodiment, the set of lifting values is limited to lifting values that are each a different power of two. The memory is configured to store parameters associated with the base parity check matrix.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: A method of operating a disk drive comprises scanning each Logical Block Address (LBA) of the disk drive to detect a read error or reading the LBA from a media defect list. The LBA may then be converted to a corresponding physical location on the media and a scan of the corresponding physical location and of nearby physical locations that are within a proximity threshold of the corresponding physical locations may be performed to find media defects. Based thereon, it may then be determined whether a media scratch is present and at least one or more data sectors associated with the media scratch may be relocated to a spare location on the media if the media scratch is determined to be present. If the media scratch is determined not to be present, only the data sector associated with the corresponding physical location may be relocated to the spare location.

Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.