Abstract: Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.

Abstract: An impedance adjustment device includes a variable capacitor unit. A microcomputer changes the capacitance value of the variable capacitor unit by switching PIN diodes included in n capacitor circuits on or off separately. Thus, the impedance on the plasma generator side when viewed from a high frequency power supply is adjusted. When changing the capacitance value of the variable capacitor unit to a target capacitance value, the microcomputer changes the capacitance value. When a predetermined period passes after the change of the capacitance value, the microcomputer changes the capacitance value again.

Abstract: A control circuit for a wearable device includes: a power supply circuit, a DC blocking circuit, and a voltage comparison circuit. The power supply circuit is connected to a high voltage end, a low voltage end, a first signal input end, a second signal input end; the DC blocking circuit is connected to the first node, the second node, and a sensor in the wearable device; the voltage comparison circuit is connected to the first node, a reference voltage end and an output end, and configured to compare voltages of the first node and the reference voltage end; and output a first control signal through the output end when the voltage of the first node is smaller than the voltage of the reference voltage end, and output a second control signal through the output end when the voltage of the first node is larger than the voltage of the reference voltage end.

Abstract: Provided is a FET resistive frequency mixing device having improved RF-LO and IF-LO isolations. The frequency mixing device includes: a field effect transistor (FET), a local oscillation matching circuit connected to a gate of the FET to transfer a local oscillation signal to the gate of the FET, a gate biasing circuit connected to the gate of the FET, a radio frequency (RF) matching circuit having a first terminal connected to a drain side of the FET and a second terminal serving as a RF terminal to receive or output a RF signal, an intermediate frequency (IF) matching circuit having a first terminal connected to the drain side of the FET and a second terminal serving as an IF terminal to receive or output an IF signal, and a series resonance circuit providing a path from the drain of the FET to ground for the local oscillation signal.

Abstract: Methods and apparatus are disclosed of a wireless power transmission system (WPTS) and wireless power receiver client (WPRC). The WPTS may directionally transmit wireless power to a first WPRC while concurrently directionally transmitting wireless data to at least a second WRPC. The WPTS and WPRC may reuse circuitry configured to transmit/receive wireless power to also transmit/receive wireless data.

Abstract: Disclosed herein are a frequency generator, which is provided with a frequency automatic correction function and is capable of reducing a frequency test time and a correction time, and a method of correcting a frequency thereof. The frequency generator includes an oscillator configured to generate an output frequency signal according to a frequency control signal, and a frequency corrector configured to generate the frequency control signal for controlling the output frequency of the oscillator using a reference frequency signal.

Abstract: A glitch filter is provided. The glitch filter receives an input signal and sets a voltage level of an intermediary input node in accordance with a state of the input signal. The glitch filter charges or discharges a switched capacitance based on the voltage level of the intermediary input node and charges or discharges a filter capacitance based on a charge of the switched capacitance. The glitch filter sets a state of an output signal based on the charge of the filter capacitance. The glitch filter includes a reset stage that at least partially filters a burst of glitches in the input signal from the output signal by controlling the charge of the switched capacitance based on the state of the input signal and the state of the output signal.

Abstract: An operational amplifier with one or more fully-differential amplifier stages has a common-mode control input. A low-frequency feedback control path is coupled between an output of the fully-differential amplifier stages and the common-mode control input to control low-frequency drift of the common-mode voltage of the output of the stages. A high-frequency feed-forward control path couples a pair of inputs of the stages to control high-frequency ripple of a common-mode voltage of the inputs of the stages. One or more of the differential amplifier stages may have a bias input that controls a direct-current (DC) bias voltage of gates of pull-up transistors of the stage that is both DC and capacitively coupled to the gates so that the stage operates with class A bias at DC and with class AB bias at high frequencies.

Abstract: Disclosed in embodiments of the present disclosure is a system for controlling a laser projector, a laser projector assembly, a terminal, a method for controlling a laser projector, a method for controlling a laser light output, a device for controlling a laser light output and a computer readable storage medium. The system includes a first drive circuit coupled to the laser projector. The first drive circuit is configured to output an electrical signal to drive the laser projector to project laser light and to turn off the laser projector when a duration of outputting the electrical signal is greater than or equal to a preset threshold.

Abstract: An embodiment apparatus comprises a switching-type output power stage, a modulator circuit configured for carrying out a pulse-width modulation and converting an electrical input signal into an input signal pulsed between two electrical levels, having a mean value proportional to the amplitude of the input signal, and a circuit arrangement for controlling saturation of an output signal supplied by the switching-type output power stage. The circuit arrangement comprises a pulse-remodulator circuit, between the output of the modulator circuit and the input of the switching-type output power stage, that is configured for supplying, as a driving signal to the switching-type output power stage, a respective modulated signal pulsed between two electrical levels, measuring a pulse width as pulse time interval elapsing between two consecutive pulsed-signal edges of the pulsed input signal, and, if the measurement indicates that the latter is below a given minimum value, remodulating the pulsed input signal.

Abstract: This invention is directed to systems and methods that track a specified stored energy level profile for a BESS in a microgrid. The systems and methods including using a control algorithm that tracks the stored energy level profile for the BESS. The controller algorithm includes a Kalman Filter design for a model-based state reconstruction to overcome sensor/communication errors during real-time operation. The latter is important to guarantee the ability of the microgrid to continue its seamless operation during periods of erroneous sensor measurements or flawed communication.

Abstract: A method for synchronizing acquisition of an analog signal value with a read signal for a state of an electrical contact of a motor vehicle. The method includes: controlling, at each start time of the first task, the power supply module so that the power supply module generates a read signal voltage pulse at the interface module input; at the same start time, triggering a counter for a predetermined duration shorter than the duration of the read signal voltage pulse; on the expiration of the counter duration, measuring the value of an analog signal generated by the interface module based on the state signal and of the read signal; and controlling, at the next start time of the second task, the power supply module so that the power supply module generates a zero voltage signal at the interface module input until the next start time of the first task.

Abstract: A temperature sensing circuit includes a current source circuit, a resistor, a bandgap voltage generation circuit, a voltage-equalizing circuit and a temperature determining circuit. The current source circuit has a first current output terminal and a second current output terminal. The bandgap voltage generation circuit includes a pair of bipolar junction transistors. The voltage-equalizing circuit equalizes voltages of a first current output terminal and the second current output terminal. The temperature determining circuit includes a sampling capacitor and a calculation circuit. The sampling capacitor samples a first voltage of a first terminal of the resistor and a second voltage of a second terminal of the resistor. The calculation circuit generates a temperature value by calculating a voltage difference between the first voltage and the second voltage.

Abstract: Described herein are a method and apparatus for a selective SYSREF (SYStem REFerence signal) scheme that is driven by an external SYSREF source for a system that may include, for example, analog blocks, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), radio frequency (RF) arrays, as well as digital blocks, which may include JESD serializer/deserializer (SERDES) Transport and Link Layer circuitry, all of which can be operating at different clock frequencies. In one aspect, synchronization of the components is achieved when an internal SYSREF for the analog blocks is keyed off the external SYSREF, but the internal SYSREF pulse used by the digital blocks is programmatically keyed off one of the periodic internal SYSREF pulses. Additionally, a mechanism is provided for synchronization of the programmatically selected internal SYSREF across different clock domains in the digital blocks.

Abstract: An interface electronic circuit between an energy harvesting stage is provided with an inductor and a charging stage, the interface electronic circuit having a regulation circuit capable of servo-controlling an average input impedance value of the interface electronic circuit to a predetermined optimum impedance value.

Abstract: A transmission device of the present disclosure includes: a driver unit that transmits a data signal with use of a first voltage state, a second voltage state, and a third voltage state interposed between the first voltage state and the second voltage state, and is configured to make a voltage in the third voltage state changeable; and a controller that changes the voltage in the third voltage state to cause the driver unit to perform emphasis.

Abstract: A filter capacitor discharge circuit includes a high-voltage terminal, a signal preparation circuit, a low-pass filter, a voltage level detector, a timer unit, and a switch unit. The signal preparation circuit receives a detection signal corresponding to an AC voltage from the high-voltage terminal, and generates a voltage signal according to the detection signal. The low-pass filter provides a filtered signal according to the voltage signal. The voltage level detector checks whether a voltage difference between the voltage signal and the filtered signal is less than a predetermined value. When the voltage difference is less than the predetermined value, the timer unit performs time calculation to accumulate a timing result. When the timing result exceeds a predetermined time, the switch unit is turned on so that the firster capacitor is discharged through the switch unit.

Abstract: An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.

Abstract: A field device comprising: a device electronic; a bus interface embodied to connect the field device to a field bus and a surface acoustic wave connecting the device electronic to the bus interface is disclosed. The bus interface includes a bus driver transmitting communication signals corresponding to digital transmission signal provided by the device electronic onto the field bus and a bus receiver receiving communication signals from the bus and providing corresponding digital reception signals to the device electronic. The surface acoustic wave transceiver transmits the digital transmission signals provided by the device electronic to the bus driver and transmits the digital reception signals provided by the bus receiver to the device electronic. Thereby, the surface acoustic wave transceiver galvanically isolates the device electronic from the bus driver and the bus receiver.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.