Abstract: Differential chopper type comparator including a switching circuit which switches between a reference signal and an input signal according to a connected first period and second period, first and second comparator circuits, and a differential comparator circuit differentially comparing the outputs of the first and second comparator circuits. Each of the first and second comparator circuits comprises a capacitor, an inverter serially connected to the capacitor, and a switch that short-circuits the input/output terminal of the inverter during the first period. The first and second comparator circuits operate in tandem such that the reference signal is input to the firs comparator circuit during the first period when the inverter is short-circuited, while conversely the input signal is input to the second comparator circuit during the first period when its inverter is short-circuited, with the reverse occurring with respect to the first and second comparator circuits during the second period.

Abstract: A hard disc drive having a digital servo system for controlling the position of a servo head on a dedicated servo surface. The servo surface is formatted in a series of consecutive frames along concentric tracks, each frame passing the servo head in a time that defines a sampling interval for the servo system. The frames contain track address and position fields for locating the servo head and location can be effected in relation to limited or extended fine control regions about the tracks via signals transmitted to a position circuit utilized to generate a servo position error from the position field. The position circuit generates a track phase code for checking track addresses generated by a track address circuit used to generate a track address from the address field.

Abstract: For responding to a shorted gate in a gate turnoff thyristor the gate electrode of which is connected by means of a controllable switch to a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, the controllable switch being arranged to conduct negative gate current in response to a thyristor turnoff command, voltage comparing means is coupled to the controllable switch for detecting when the switch is conducting negative gate current of relatively high magnitude, timing means is active for a predetermined interval following the start of said thyristor turnoff command, and logic means is operative to cause the switch to stop conducting negative gate current if the voltage comparing means detects high gate current at the end of such interval.

Abstract: A comparator circuit is provided that determines whether a given value is within a selected compare range. The comparator circuit electronically implements a Ling Adder algorithm to perform comparisons. The circuit operates at a high speed and requires fewer components compared to circuitry implementing a conventional carry look ahead algorithm. The circuit may be implemented in CMOS technology.

Abstract: A gamma correction circuit including a differential amplifier for generating a current which decreases as an input voltage increases; a current control circuit for generating a current which is zero when the input voltage is below a first set value, increases as the input voltage increases when the input voltage is in a range from the first set value and a second set value, and becomes constant when the input value exceeds the second set value; and a circuit for generating a voltage proportional to a sum of the above-mentioned currents.

Abstract: Methods and devices are disclosed for selectively varying the load to a photodetector such as a phototransistor which forms part of a photosource/photodetector pair and for selectively using to advantage or compensating for the parasitic capacitance of the photodetector to permit reductions in power, conversion of fixed signal thresholds to software controlled digital hysteresis, automatic adjustment and compensation for unmatched photosources and associated photodetectors, and adjustment of fixed voltage thresholds.

Abstract: An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A.sub.IN is pulled to V.sub.SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).

Abstract: A peak detector for rapidly following the peak voltage of a pulsed input signal without significant droop between pulses. The peak detector has a master section which selectively controls the droop rate of a slave section. The output of the slave section is the output of the peak detector. The master section droop is determined by a resistor, which may be disconnected therefrom to hold the peak of the input signal.

Abstract: An auto-tracking system for a helical scan type magnetic recording/reproducing unit comprises a synchronizing signal separating circuit from video signals on a running magnetic tape reproduced by a rotary video head, a periodicity variation measuring and comparing circuit in the synchronizing signals separated in the synchronizing signal separating circuit, and a tracking control means which controls the running condition of the magnetic tape with reference to a phase difference between a reference signal in association with the rotary video head and a signal representing the running condition of the magnetic tape and changes tracking by a predetermined amount in response to the periodicity variation measured by the measuring and comparing circuit so as to minimize the periodicity variation measured by the same, thereby an optimum tracking position is obtained without being interfered by cross-talks between the adjacent tracks.

Abstract: Method and circuitry for decreasing the recovery time of an MOS differential voltage comparator after an input voltage overdrive. At the beginning of a comparison cycle a reverse voltage is momentarily applied between the gates and sources of the input pair of source-coupled MOS transistors of sufficient magnitude to form a charge accumulation layer in the channel region of each of the transistors. Operating the differential voltage comparator in such manner substantially decreases the time required for the transistors to recover from an imbalance in their electrical characteristics caused by the input voltage overdrive.

Abstract: An anti-clipping mixer circuit is provided within an integrated circuit. The mixer circuit allows for the independent level control of each input signal, thereby allowing the optimization of the signal-to-noise ratio. A master level control is provided to limit the overall combined output signal to a level below the operational amplifier's maximum voltage level. A control circuit may be used to automatically adjust the input signal levels as well as the combined output signal level.

Abstract: In a display control apparatus for controlling a display unit for displaying operation performance of an arithmetic processor with reference to a performance signal representative of the operation performance, a first producing circuit (28) produces a peak signal in compliance with a count signal produced by a counting circuit (22) which is for counting an operation number of operation of the arithmetic processor. A comparing circuit (31) carries out comparison between the peak and the performance signals to produce a result signal representative of a result of the comparison. A second producing circuit (29) produces the performance signal with reference to the result signal.

Abstract: A sample-and-hold circuit comprising a diode circuit including four diodes connected in series, an input circuit connected to a first node of the first and third diodes and a second node of the second and fourth diodes, first and second output terminals connected to a third node of the first and second diodes and a fourth node of the third and fourth diodes, two capacitors connected to the third and fourth nodes, respectively, and a current mirror circuit having a first terminal connected to the input circuit, a second terminal connected to the first node, and a third terminal connected to the second node, for supplying to the second and third terminals, a DC bias current and a dynamic current corresponding to the slew rate of the input signal flowing through the first terminal of the current mirror circuit.

Abstract: A double polysilicon dual gate LDMOSFET structure combined with a detecting circuit can be used to reduce the ON state resistance and without degradation of the breakdown voltage of the LDMOSFET. In the ON state, a drift region is driven into accumulation. In the OFF state, a gate is made to float and thereby avoid degradation of the breakdown voltage. A switch or transistor is modulated to either allow applied voltage to bias the gate for enabling the drift region to be driven into accumulation or to cause the gate to float to prevent the driving of the drift region by the voltage.

Abstract: A memory array formed from single transistor flash cells employs prevention circuitry for minimizing the effect of any floating gates in an over-erased state when accessing data stored in the memory array device. The prevention circuit includes a column line coupling a current limiting device in each row together in a common column. The memory array device also employs a row current limiting device which couples that row of flash cells to the erase potential. The second row switching means is activated to prevent a false signal generated by an over-erased flash cell in the same column as a selected flash cell being accessed for data from masking the data retrieval from the desired flash cell.

Abstract: A switching arrangement for an RF-GTO is specified. It comprises a latching-type semiconductor component (GTO) of familiar construction. The circuit for turning off the semiconductor component (GTO) is designed in such a manner that the turn-off gain I.sub.A /I.sub.G, peak is distinctly less than 3 and, in particular, less than or equal to 1. During the turning-off, the drive is hard, that is to say has a high rate of increase dI.sub.G /dt and high current. A capacitance (C.sub.p) is connected directly in parallel with the semiconductor component (GTO).

Abstract: A level converting circuit for converting input signals into different level signals which enables a stable high speed operation to be realized and which may be used advantageously for driving, above all, liquid crystal display devices. Voltage clamping circuits 1 and 2 are provided at signal input terminals of n-MOS transistors 3 and 4 connected to the drains of pMOS transistors 5 and 6 connected in a current mirror configuration. By these voltage clamping circuits 1 and 2, the input levels of the nMOS transistors 3 and 4 are shifted to higher levels, as a result of which a current larger than that in the conventional circuit flows through the nMOS transistors 3 and 4 to speed up charging and discharging. Stable driving may be enabled even when the nMOS transistors 3 and 4 are formed as thin film field effect transistors for use with liquid crystal display elements.

Abstract: A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state.

Abstract: A method of manufacturing a liquid crystal display panel by forming a plurality of spaced scan lines, a plurality of spaced orthogonal data lines, and contact pads for each line on a substrate. Forming an electrostatic discharge line and light controlled discharge devices, each device being joined to the discharge line and a contact pad. Next illuminating the discharge devices and completing the fabrication of the array of optical display elements on the substrate associated with scan and data lines, blocking the light from discharge devices and electrically testing the array. Then again illuminating the discharge devices while assembling a second substrate over the first substrate and inserting the liquid crystal material therebetween.

Abstract: An optical connector assembly (1) for connecting an optical fiber (9), an optical element (4) (light-emitting element or light-receiving element), and an electric circuit together. A bolt (32) of an optical fiber-mounting fitting in which the optical fiber (9) is inserted in the hole of an electic seal (32) and a bolt (31), is screwed into a threaded hole formed in a housing (2) of the plug (1) that accommodates the optical element (4) in order to couple the optical fiber (9) to the plug (1). The connection between the optical element (4) and the electric circuit is accomplished by a jack (20) and the plug (1) is provided with a lock mechanism based on a push-type lever (20), featuring improved sealing performance against water, oil, dust and dirt.