Abstract: A multiport memory system has a plurality of data input/output ports, a plurality of memory banks, and a switching network for connecting the ports and the memory banks. A page address is transferred by way of a data line of the switching network and an address calculation is performed in each memory bank so that data can be read out of and written in to continuously via the plurality of ports.

Abstract: An inter-processor communication module is inserted into a slot of an equipment rack of the type used to connect I/O modules to system processors in a programmable controller. Using two of the inter-processor communication modules in two respective racks, a supervisory processor is connected to two respective local area processors in a distributed control system. The inter-processor communication module has a serial channel controller that connects to the supervisory processor through a serial I/O port and a serial communication channel to communicate blocks of I/O status data. The serial channel controller is coupled to a backplane controller through a common memory and arbitration circuitry to exchange blocks of I/O status data. The backplane controller, which is also a part of the inter-processor communication module, plugs into the backplane of the rack and exchanges blocks of I/O status data with a local area processor.

Abstract: Method and apparatus for dynamically providing virtual storage resources to an operating system control program in a computing complex where the control program controls the concurrent execution of multiple virtual machines confer on the control program the capacity to gain access to virtual storage resources through the creation of pseudo-virtual machine control blocks that are available only to the control program.

Abstract: A communication system includes a processor, memory circuits and a plurality of interfaces for interfacing to data devices. The processor services the interfaces using an interrupt bus including unidirectional inbound and outbound buses. The inbound bus includes one lead for each interface, with each lead having a fixed priority level assigned by the processor. Each interface has access to all leads of the inbound bus. The processor sends commands over the outbound bus to dynamically control the connection of an interface to a lead of the inbound bus.

Abstract: A magnetic disc unit device controlling system and method are disclosed in which a magnetic disc unit controller for selecting any one of a plurality of magnetic disc units and exchanging information between a computer and a selected disc unit is provided with a memory for storing substitute track tables indicative of substitute track positions corresponding to defective tracks in the disc units. The substitute track table is accessed prior to sending positioning instructions to the selected disc unit. If a substitute track exists, the address of the substitute track is sent to the selected disc unit as a positioning instruction. If there is no substitute track, the received positioning information is passed to the selected disc unit as a positioning instruction.

Abstract: A digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separate column for each PPM port. Each PPM preferably includes at least three ports to permit parallel transfer of instructions and data to the PPM's. The ports of the PPM's are also connected to segmented lateral transfer buses which operate in conjunction with the internal bus switching of the PPM's to permit tandem ALU operation.

Abstract: In a multiprocessor system, a program's execution that is controlled by controlling an extended process that spans a plurality of processors. The extended process comprises an user process on one processor for executing object code of the program and stub processes each on an individual one of said remaining processors for accessing system resources required for execution of the program. Each stub process gives the extended process access to the resources associated with the processor executing the stub process. Further, a stub process is unique to one particular extended process. Each stub process is interconnected to the user process by an individual virtual communication channel. The virtual communication channels are identified in each process by a port table that is unique to an individual process. When the user process accesses a local file, the access is through a user file table, a system file table, and an inode table.

Abstract: A system has a central processor and multiple addressable terminals connected by a communication cable. The terminal itself contains a list of candidate addresses it can use. The terminal determines which of the candidate addresses are already in use by other terminals, and selects one (or more) for itself that is not in use.

Abstract: A system by which a number of central processing units (CPU's) may be used completely independently of one another, and yet by which any CPU within the system may communicate with any other CPU in the system. The implementation of the system requires each CPU to be physically connected only to its own bus and to the bus of one other CPU even if there are many CPU's and buses in the system. This enables each CPU in the system to have access to all of the buses of all of the other CPU's in the system.

Abstract: An accelerator module for a data flow computer includes an intelligent memory. The module is added to a multiprocessor arrangement and uses a shared tagged memory architecture in the data flow computer. The intelligent memory module assigns locations for holding data values in correspondence with arcs leading to a node in a data dependency graph. Each primitive computation is associated with a corresponding memory cell, including a number of slots for operands needed to execute a primitive computation, a primitive identifying pointer, and linking slots for distributing the result of the cell computation to other cells requiring that result as an operand. Circuitry is provided for utilizing tag bits to determine automatically when all operands required by a processor are available and for scheduling the primitive for execution in a queue.

Abstract: A data link processor (peripheral-controller), for managing data transfers to/from multiple disk drive modules, provides a hardware self-test operation to its subsystem card units when it is powered on. The data link processor momentarily disables its interfaces to the peripheral disk drives and the host computer to execute test operations and to indicate either the integrity condition or fault condition of its card units. Each card unit also has a pushbutton for self-test initiation and a local light-emitting diode which lights up and stays lit up if the card unit is misfunctioning to indicate a failed card unit. Further, the connected host computer can initiate the self-test operation for the peripheral-controller for integrity testing.

Abstract: A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.

Abstract: In an industrial process control system, in which a plurality of remote stations interconnected by a communications link each control and manage a plurality of input/output devices, each remote station comprises a primary data processor and a back-up data processor. The primary data processor normally exercises control over and manages the input/output devices, but, should the primary data processor fail, the back-up processor takes over management and control of the input/output devices. Periodically, the primary data processor transfers status data relating to its operation in the control of the input/output devices to the back-up data processor via a dual ported memory connected between the two processors. The back-up processor maintains a record of the status data and updates its record of the status data with the periodically transferred copy of the status data.

Abstract: A processor and disk controller are arranged to operate with either of two types of disk drive, a drive for a five and one-fourth inch disk or a drive for an eight inch disk, and a method and apparatus are provided to test a port to detect which type disk is connected. The disk drives do not directly signal their type, and in one operation this information is derived from "drive ready", signals that are supplied separately by each disk type. In an alternative method and apparatus, this information is derived by a test in which the clock speed is changed.

Abstract: In a system wherein a plurality of processors have instruction sets which are different at least in part from one another, it is possible for any processor to generate the object program. This is accomplished by generating object program sections inherent to the processors and the remaining sections which are common to the processors in the same object program.

Abstract: A method for serializing process access to shared resources utilizing low-level atomic functions to maintain control structures in which noncontiguous words must be modified at two different times. The atomic functions require an initiation operation partitionable from a completion operation. Each process requesting access to the shared resource performs the initiation operation, which begins modification of a control structure. The completion operation may be performed by the original process if there is no resource conflict. If, however, another process is currently modifying the control structure, then the task of performing the completion operation is passed to one of the concurrently-accessing processes.

Abstract: A character data processor for a videotex or teletext system includes a microcomputer section, a self data processing unit and a read/write memory. A memory access period for the memory exists in one read/write cycle of character data packets. Data processing unit responds to a first pulse indicating the start of the memory access period and to a second pulse indicating the end of the memory access period. Data processing unit includes an address change circuit which stores initial address data and transfers address data stored therein to the memory according to a transfer pulse. The content of address data is changed by a change pulse. A data register relays data transferred between the microcomputer section and the memory. A generator circuit generates the transfer pulse, the change pulse and a clock pulse according to the generation of the first and second pulses and a detection signal. A detection circuit responds to prescribed data indicating the run length of character data.

Abstract: A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Abstract: In an apparatus wherein a memory is subdivided into plural storage areas, and predetermined data are adapted to be written into respective ones of the storage areas, a method of reconfiguring the storage areas of the memory. The leading addresses of the respective storage areas and the sizes of blank portions of the respective storage areas are stored while it is discriminated whether a blank portion exists in a predetermined one of the storage areas. When there is no blank portion or substantially no blank portion in the predetermined storage area, the blank portions of the remaining storage areas are reduced in size on the basis of the leading addresses and the sizes of the blank portions. The predetermined storage area is enlarged by an amount equal to the amount of blank portion reduction effected in the remaining areas.

Abstract: A system for generating a mask pattern for a vector data processor is described having at least a mask register and a vector register in which, when the value of the mask register is "1", a calculation is executed for the corresponding element of the vector register, and when the value of the mask register is "0", a calculation is not executed, in accordance with the so-called calculational mask function. The system includes: a designation unit for designating sequential i elements of "0" or "1" from the head element of the mask register, and the subsequent sequential j elements of "1" or "0"; a control unit for rendering the i elements to be "0" or "1", the j elements to be "1" or "0", and the remaining entire elements to be all "0's" or all 1's, when "i" plus "j" is smaller than a vector length which is the object of calculation of a vector data operand for use in a vector instruction; and a desired mask pattern of "0" or "1" is able to be generated in the mask register.