Abstract: Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.

Abstract: The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Abstract: Methods and systems for improving segmentation of a digital model of a patient's dentition into component teeth.

Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enabling a variable refresh rate on a display. One of the methods includes receiving, from a content presentation device, a first signal set to a first value; completing generation of first visual content; and after completing the generation of the first visual content, determining that the first signal is set to the first value and a second threshold duration of time has not expired; sending, to the content presentation device, the first visual content, wherein sending the first visual content causes the content presentation device to change the first signal from the first value to the second value; and after sending the first visual content, receiving, from the content presentation device, the first signal set to the second value.

Abstract: A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.

Abstract: A CAD plotting method of equally dividing an optional angle which is capable of reducing a plotting error so as to be fitted for a practical use with a simple plotting procedure, as compared to a conventional plotting method.

Abstract: Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.

Abstract: An apparatus to facilitate thread scheduling is disclosed. In one embodiment the apparatus includes a processor comprising a plurality of multiprocessors comprising single-instruction multiple thread (SIMT) execution circuitry to simultaneously execute multiple threads, a shared local memory to be shared by the multiple threads, and scheduling hardware logic to schedule the multiple threads in a thread group for execution across the plurality of multiprocessors in accordance with barrier data. The instructions of the multiple threads are to produce shared data to be stored in the shared local memory when executed by the plurality of multiprocessors, wherein additional instructions of at least a first thread of the multiple threads are to use the shared data, and wherein, in accordance with the barrier data, the first thread is to wait for other threads of the multiple threads to finish producing the shared data before executing the additional instructions.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is a valid page that is cleared to a clear color and graphics pipeline circuitry to bypass a memory access for the first virtual page based on the first page table entry in response to determination that the first virtual page is cleared to the clear color and determine a color associated with the first virtual page without performing a memory access to the first virtual page.

Abstract: A method for compressing display data is disclosed. The method comprises performing a wavelet transformation to obtain a general approximation coefficient and a plurality of detail coefficients for a group of pixels; determining whether to prioritise transmission of the general approximation coefficient over transmission of the detail coefficients based on whether there are sufficient resources available to enable a corresponding image frame to be ready for display and/or based on a time since the detail coefficients for a corresponding group of pixels were previously transmitted.

Abstract: A digital integrated circuit with embedded memory for neural network inferring may include a controller and a matrix of processing blocks and cyclic bidirectional interconnections, where each processing block is coupled to 4 neighboring processing blocks regardless of its position in the matrix. A cyclic bidirectional interconnection may transmit every processing block's output to its upper, lower, left, right neighboring blocks or to its cyclic neighbors of the same row or column in replacement of any missing upper, lower, left or right neighbors. Each processing block may include invariant word buffers, variant word buffers, a multiplexer, and a processing unit. The multiplexer may select one of the 4 neighbor processing blocks' outputs. The processing unit may accept as inputs the multiplexer's selected value, a selected value from the variant word buffers and a selected value from the invariant word buffer and produce output which acts as the processing block's output.

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i?1 layer of the binary neural network.

Abstract: The disclosed technology includes a computerized ionospheric tomography method based on vertical boundary truncation rays, which relates to the technical field of computerized ionospheric tomography (CIT). The method includes: obtaining an initial ionospheric electron density (IED) of each voxel in a target region and an ionospheric total electron content (TEC) value along a propagation path from a global navigation satellite system (GNSS) satellite; extending the target region so that GNSS stations within a certain range beyond the target region are encompassed within the target region; for GNSS stations within a certain range in the target region, calculating a vertical boundary truncation TEC value; for the GNSS stations within the target region, calculating a vertical boundary truncation TEC value; and building a three-dimensional CIT model based on the vertical boundary truncation TEC values PrTEC and PsTEC.

Abstract: A method of obtaining a 3D model of a subject includes capturing a plurality of images of the subject by an image capture device, associating respective ones of the plurality of images with a timestamp and unique identification number, transmitting image capture data comprising the timestamp and the unique identification number to an external server, receiving a transmission comprising the unique identification number, and, responsive to receiving the transmission, transmitting a first image of the plurality of images that is associated with the unique identification number.

Abstract: An embodiment for adjusting digital content in a flexible display device is provided. The embodiment may include receiving data relating to a position and orientation of a reference device relative to a user. The embodiment may also include identifying an orientation of a display surface of a mobile device and a relative position of the mobile device relative to a viewing direction of the user. The embodiment may further include identifying an optimal viewing angle of display content on the display surface of the mobile device. The embodiment may also include in response to determining the display content is not able to be displayed as a hologram, aligning the display content as text based on the optimal viewing angle. The embodiment may further include presenting the aligned display content as text to the user.

Abstract: An artificial neural network (ANN) generates a base expanded matrix that represents an output of a layer of the ANN, such as the output layer. Values in each row are grouped with respect to a set of network parameters in a previous layer, and a sum of the values in each row produces an output vector of activations. The ANN updates the values in at least one column of the expanded matrix according to parameter updates, which results in an updated expanded matrix or an update expanded matrix. An error or a total cost can be computed from the updated expanded matrix or the update expanded matrix. Nonlinear activation functions can be modeled as piecewise linear functions, and a change in an activation function's slope can be modeled as a linear update to an expanded matrix. Parameter updates can be constrained to a restricted value set in order to simplify update operations performed on the expanded matrices.

Abstract: An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data.

Abstract: A processor includes a register, a non-zero weight value selector and a multiplier. The register holds a first group of weight values and a second group of weight values. Each group of weight values includes at least one weight value, and each weight value in the first group of weight values corresponding to a weight value in the second group of weight values. The non-zero weight value selector selects a non-zero weight value from a weight value in the first group of weight values or a non-zero weight value in the second group of weight values that corresponds to the weight value in the first group of weight values. The multiplier multiplies the selected non-zero weight value and an activation value that corresponds to the selected non-zero weight value to form an output product value.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.