Abstract: A barrier coating is formed on a polymeric article, such as on the interior of a thermoplastic container. An oxidizing gas is converted to a plasma in a plasma chamber remote from the treatment chamber. The resulting plasma-activated oxidizing species are delivered to the interior of the container. An organosilicon reactant vapor is separately but simultaneously delivered to the interior of the container so that the organosilicon vapor and oxidizing active species mix within the container. An electric qfield is also applied to the container, so that the reaction products are deposited under the influence of the electrical field to form the barrier coating.

Abstract: A method of forming an FET device starts by forming a sacrificial layer over a semiconductor substrate and an outer buried contact region is produced by ion implantation into the substrate, followed by stripping the sacrificial layer, forming a gate oxide layer, and depositing polysilicon over the gate oxide layer. Then, etch an inner buried contact opening through the polysilicon and the gate oxide layer down to the substrate over the outer buried contact region forming an etched buried contact opening. Implant dopant into the substrate through the inner buried contact opening in the second mask to dope the substrate forming the inner buried contact region within the outer buried contact region self-aligned with the etched buried contact opening. Form a blanket, second polysilicon layer over the gate oxide layer reaching down through the etched buried contact opening into electrical and mechanical contact with the inner buried contact region.

Abstract: A method for manufacturing stacked dynamic random access memory using reduced photomask steps was achieved. The invention utilizes two masking steps for forming the array of stacked capacitors and bit line contacts. One of the masking steps is used to concurrently form the bit line contact openings and to define the capacitor top electrode area for the stacked capacitors. After forming the array of field effect transistors by conventional means, an array of capacitor bottom electrodes is patterned from an N.sup.+ doped polysilicon layer using the first photoresist mask and plasma etching. An interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped second poly-silicon layer and insulating layer are deposited. The insulating layer and second polysilicon layer are patterned with a second photoresist mask and plasma etched to concurrently form the bit line contact openings and to define the capacitor top electrode plate.

Abstract: A plasma reactor has plural dielectric gas injection tubes extending from a gas injection source and through a microwave guide and into the top of the reactor chamber. The semiconductor wafer rests near the bottom of the chamber on a wafer pedestal connected to a bias RF power source which is controlled independently of the microwave source coupled to the microwave guide. The microwaves from the waveguide ignite and maintain a plasma in each of the tubes. Gas flow through the tubes carries the plasmas in all the tubes into the chamber and into contact with the wafer surface.

Abstract: A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.

Abstract: A method of fabricating a honeycomb shape capacitor is provided. A first polysilicon layer having a contact to a device area is formed over an insulation layer. A first oxide layer is formed over the first polysilicon layer. A layer of hemispherical particles, is formed over the first oxide layer. The first oxide layer is anisotropically etched using the hemispherical particles as a mask forming pattern of vertical extensions. A doped polysilicon layer is formed over the hemispherical particle layer and the pattern of vertical extensions. The doped polycrystalline layer and the hemisphere particle layer are etched back to expose the tops of the vertical extensions of the first oxide layer. The vertical extensions of the first oxide layer removed by a selective etch forming honeycomb holes in the doped polysilicon layer thereby forming the honeycomb shaped bottom storage electrode.

Abstract: A method for fabricating a capacitor of a semiconductor device which stabilizes the operation of electrodes of the capacitor and improves the operational characteristic and reliability of the semiconductor device.

Abstract: A microwave plasma processing apparatus comprises a vacuum processing chamber, a substrate disposed within the vacuum processing chamber, a microwave guide coupled to the vacuum processing chamber, and fins for dividing a microwave in the electric field direction. The length of fins are different such that the uniformity of the film thickness distribution on the substrate of large area can be improved.

Abstract: A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second N-MOS transistors on the silicon substrate, and a P-MOS transistor on the silicon well. The source and drain regions of each of the P-MOS transistor and the first and second N-MOS transistors each have a polysilicon plug making contact therewith. Each polysilicon plug is isolated one from another by nitride spacers, has the same doping as the region with which it makes contact, and is self-aligned to the nitride spacers lining the passage of the polysilicon plugs to their respective contacts on either the silicon substrate or the silicon well. The self-aligned nature of the polysilicon plugs is due to the nitride spacers formed by etchant selectivities and photoresist masks.

Abstract: A plasma processing apparatus comprises a processing container, a waveguide tube for guiding microwaves generated by a microwave generator, and a flat antenna member connected to the wave guide and disposed in the container to face a semiconductor wafer supported in the container. The antenna includes a plurality of short slits concentrically or spirally arranged in the antenna. The slits are spaced apart in the widthwise direction at intervals of 5% to 50% of a guide wavelength of the microwave, and each of the slits has a length of +30% of the guide wavelength centered with respect to half of the guide wavelength.

Abstract: On the principal surface of an Si semiconductor substrate, a field oxide film is formed defining an active region. On the active region, an insulated gate structure is formed including a gate oxide film and a polycrystalline Si layer. At the same time, a lower capacitor electrode of the polycrystalline Si layer is formed on the field oxide film. The surface of the polycrystalline layer is oxidized to form an insulating film. Another polycrystalline Si layer is deposited covering the insulating film. A mask is formed over the lower capacitor electrode. By using this mask as an etching mask, anisotropic etching is performed to leave an upper capacitor electrode and side wall spacers on the side walls of the gate electrode and lower capacitor electrode.

Abstract: A heat-resistive electrode material substantially consisting of 40 to 60 wt % of at least one of ZrB.sub.2 and TiB.sub.2, 20 to 50 wt % of BN, and not more than 30 wt % of AlN is disclosed. This heat-resistive electrode material is used in at least portions of electrodes of an apparatus having a plasma generating unit, e.g., an ion source, a plasma etching apparatus, or a plasma CVD apparatus, that contacts a plasma.

Abstract: In a plasma processing apparatus having an upper electrode and a lower electrode in a vacuum chamber, a substrate receiving face of the lower electrode is formed to have a same convex surface as a deflected face of a substrate on condition that surface of the substrate is freely supported on an circumference thereof, and a uniform pressure is applied to the back of the substrate.

Abstract: A head drum is coated with double films, each having different characteristics, by forming a first diamond-like hard carbon film of high degree of hardness and then forming a second diamond-like hard carbon film of a lower degree of hardness thereon. The degree of hardness of the second film is lower than that of the first film. The double coating is performed by means of a synthesizing apparatus which comprises a reactor consisting of a power supply electrode, a workpiece support and an annular ground electrode spaced from the stacked head drums by a predetermined distance.

Abstract: A side-by-side capacitor structure in which the side-by-side capacitors are formed using a common dielectric layer, with a capacitor plate electrode shaped as an electrostatic shield for preventing stray capacitance between the side-by-side capacitors. More particularly, a substrate of semiconductive material has first and second contact areas on its top surface. First and second electrodes are located parallel to the top surface of the substrate of semiconductive material, but spaced therefrom by an electrically insulating layer that has first and second contact holes extending therethrough from the first and second contact areas to the first and second electrodes respectively. These contact holes are each filled with a respective conductive plug. The electrically insulating layer has a trench in its surface with first and second sides respectively aligned with an edge of the first electrode and with an edge of the second electrode.

Abstract: An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

Abstract: Alignment structures in gaps between patterned features, such as polysilicon wordlines or metal contacts, have a selective effect on various processes to promote self-alignment. The various processes include ion implants for code programming, formation of via cuts, and the polycide process of forming composite layered gates. The alignment structures improve these processes by having a selective effect during etching, deposition, and ion implants. Thus, in one example, to prepare a ROM array for code programming using the ion implantation process, the alignment structures or ion barrier walls are formed between the plurality of wordlines. These ion barrier walls, typically silicon nitride or silicon dioxide, have a height above the substrate that is greater than the height of the wordlines. When viewed from a direction orthogonal to the substrate, only the ion barrier walls and wordlines are visible.

Abstract: The present invention is directed to a plasma treating apparatus, for generating plasma in a dielectric container and for treating the surface of a substrate with the plasma generated, which includes a hot air heating system for heating the dielectric container by blowing hot air to a central location on the outside surface of the dielectric container.The present invention is further directed to a plasma treating method for generating plasma in a dielectric container and for treating the surface of a substrate with the plasma generated which includes hot air heating for heating the dielectric container by blowing hot air to the outside surface of the dielectric container to a temperature at which a thin film does not deposit on the inside surface of the dielectric container.

Abstract: A process apparatus whose chamber can be cleaned in a short time while not being exposed to air at all. First and second electrodes (107,105), are provided in a vacuum vessel (108). A first high-frequency power supply (112) having a first frequency is supplied to the first electrode (107), and a second high frequency power supply (101) having a second frequency different from the first frequency is provided. An impedance means and a means for connecting the second high frequency power supply to the second electrode are also provided. A means for supporting a wafer (106) is disposed on the second electrode (105), and a gas introduced into the vacuum vessel (108) is turned into a plasma by the first and second high-frequency powers.

Abstract: In CVD processes susceptors can be made of a thermally conductive ceramic such as aluminum nitride which has superior durability with respect to fluorine plasma. Such aluminum nitride susceptors can include an embedded heater element and/or embedded ground or RF electrodes which as a result of their embedment are protected from the deleterious effects of the processing chamber environment. The conductors leading to these elements are protected from exposure to the process chamber environment by passing through a cylindrical member filled with inert gas supporting the wafer support plate of said susceptor. Alternately, the conductors leading to these elements can be run through passages in a hermetically sealed stem supporting the susceptor wafer support plate. The stem passes through the wall of the processing chamber so that connections to the susceptor wafer support plate can be made outside the processing chamber.