Patents Examined by José H. Alcalá
  • Patent number: 6974916
    Abstract: In a laminated ceramic electronic component, the sectional size of via-hole conductors extending through thicker ceramic layers is larger than that of via-hole conductors extending through thinner ceramic layers. This makes it possible to facilitate filling of a conductive paste for the via-hole conductors having a larger height and to inhibit a conductive paste for the via-hole conductors having a smaller height from being lost after filling.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: December 13, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Norio Sakai
  • Patent number: 6914196
    Abstract: A reel-deployed printed circuit board for chip-on-board (COB) packages and a method for manufacturing COB packages using the reel printed circuit board are disclosed. The novel circuit board comprises an elongated, flexible base board and a plurality of unit boards defined within it by a plurality of slits cut through it. Each unit board comprises a plurality of bonding pads on its top surface, a plurality of contacts on its bottom surface, and a plurality of via holes that electrically connect the contacts to the bonding pads. The circuit board further comprises connection bars that connect the unit boards to the flexible base board. The method for manufacturing COB packages using the reel-deployed printed circuit board comprises the steps of forming the reel printed circuit board, attaching a semiconductor chip to it, connecting the semiconductor chip to the bonding pads, encapsulating the semiconductor chip, and separating the COB packages from the reel printed circuit board.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung Dae Cho
  • Patent number: 6906265
    Abstract: A cabled conductor comprises a plurality of transposed strands each comprising one or more preferably twisted filaments preferably surrounded or supported by a matrix material and comprising textured anisotropic superconducting compounds which have crystallographic grain alignment that is substantially unidirectional and independent of the rotational orientation of the strands and filaments in the cabled conductors. The cabled conductor is made by forming a plurality of suitable composite strands, forming a cabled intermediate from the strands by transposing them about the longitudinal axis of the conductor at a preselected strand lay pitch, and, texturing the strands in one or more steps including at least one step involving application of a texturing process with a primary component directed orthogonal to the widest longitudinal cross-section of the cabled intermediate, at least one such orthogonal texturing step occurring subsequent to said strand transposition step.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: June 14, 2005
    Assignee: American Superconductor Corporation
    Inventors: Gregory L. Snitchler, Jeffrey M. Seuntjens, William L. Barnes, Gilbert N. Riley, Jr.
  • Patent number: 6871396
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 6835895
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 28, 2004
    Assignee: IBIDEN Co., Ltd.
    Inventors: Motoo Asai, Yasuji Hiramatsu
  • Patent number: 6796028
    Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: September 28, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Syed Sajid Ahmad
  • Patent number: 6794585
    Abstract: A method includes the steps of forming a first metal foil (82) on a surface of an insulator substrate (1a), drilling, with a thermosetting resin film (84) temporarily fixed to an opposite surface of the substrate, a through hole (86) simultaneously in the first foil, the substrate, and the resin film, simultaneously heating and vacuum-pressing the first foil, the substrate, the resin film, and a second metal foil (87) brought into contact with the resin film to obtain an intermediate board in which a bottom of the through hole is covered with the second foil and has a corner with a corner rounded portion (93) formed by the resin film, and forming a metal plating layer (95) on the first and the second foils, on the bottom and an inner wall of the through hole, and on the corner rounded portion to obtain a final printed wiring board.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: September 21, 2004
    Assignee: Japan Radio Co., LTD
    Inventors: Shigetoshi Abe, Tomoko Kato, Yasuo Sato, Takashi Itagaki, Kenji Matsumoto
  • Patent number: 6781064
    Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: August 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
  • Patent number: 6778406
    Abstract: Resilient contact structures provide electrical interconnection between a semiconductor die and another electronic component. Multilayered packaging may be formed on the semiconductor die, and the resilient contact structures may be formed on portions of one or more of the layers. Heat dissipating structures may be provided on the die.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: August 17, 2004
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 6765151
    Abstract: This invention relates to a practical superconducting conductor based upon biaxially textured high temperature superconducting coatings. In particular, methods for producing flexible and bend strain-resistant articles and articles produced in accordance therewith are described which provide improved current sharing, lower hysteretic losses under alternating current conditions, enhanced electrical and thermal stability and improved mechanical properties between otherwise isolated films in a coated high temperature superconducting (HTS) wire. Multilayered materials including operational material which is sensitive to bend strain can be constructed, in which the bend strain in the region in which such operational material is located is minimized. The invention also provides a means for splicing coated tape segments and for termination of coated tape stack ups or conductor elements.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: July 20, 2004
    Assignee: American Superconductor Corporation
    Inventors: Leslie G. Fritzemeier, Cornelis Leo Hans Thieme, Steven Fleshler, John D. Scudiere, Gregory L. Snitchler, Bruce B. Gamble, Robert E. Schwall, Dingan Yu, Alexander Otto, Elliott D. Thompson, Gilbert N. Riley, Jr.
  • Patent number: 6762367
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Patent number: 6750403
    Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: June 15, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Melvin Peterson
  • Patent number: 6740821
    Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, David Kao
  • Patent number: 6734375
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 6734369
    Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Bailey, Michael John Shea, Gerald Wayne Swift
  • Patent number: 6727435
    Abstract: A powerplane for use in a backplane power distribution system. The backplane includes a conductive sheet for distributing power from a power source to a load. The powerplane further includes source locations and load locations for coupling the conductive sheet to a power source and a load. The conductive sheet has resistances with appropriate spacing and dimensions so that the resistance near the source locations is greater than the resistance farther away from the source locations. Thus, current is shared more evenly between all the load locations, and the voltage difference between distant load locations and near load locations is reduced to near zero.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Patrick Kevin Egan, Barry Lee Shepherd
  • Patent number: 6727436
    Abstract: A shielded interconnect bus crossover useful in interconnecting MEM devices with control signal sources or the like and a method of fabricating such a shielded interconnect bus crossover are disclosed. In one embodiment, a shielded interconnect bus crossover (10) includes a plurality of base pads (44A-C) and a plurality of support columns (74) extending upward from the base pads (44A-C) through holes formed in an interconnect bus shield (78) overlying a plurality of interconnect bus lines (42). The support columns (74) support a two layer elevated crossing line (92/112) in a spaced relation above the interconnect bus shield (78). The two layer elevated crossing line (92/112) is oriented transverse to the direction of the interconnect bus lines (42) and is located within the perimeter of a two layer rectangular crossing line shield wall (96/116).
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: April 27, 2004
    Assignee: MEMX, Inc.
    Inventors: Stephen Matthew Barnes, Murray Steven Rodgers
  • Patent number: 6723926
    Abstract: A mounting configuration of electric and/or electronic components, in particular electrolytic capacitors, on a printed circuit board is described. The printed circuit board is formed by at least two metallic plates insulated electrically from one another by an insulating layer that preferably conducts heat well and has holes for the connecting pins of the electric and/or electronic components. Through which holes the connecting pins are plugged and connected electrically to the respectively associated metallic plate.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: April 20, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kurt Gross, Volker Karrer, Michael Kirchberger, Stefan Kulig, Gunter Ludwig, Hans Rappl
  • Patent number: 6717065
    Abstract: An electric contact using resin solder is connected to a printed circuit board, which has a conductor provided on a surface thereof. This electric contact comprises a leg, which contacts the conductor of the printed circuit board, and a connecting part, which is connected to the conductor of the counterpart member. At least a part of the leg, which contacts the conductor of the printed circuit board, is made of a lead-free ultrahigh-conductive plastic being a conductive resin composite. An electric connector includes the electric contact and an insulating housing, which holds the electric contact so that the part of the leg, which contacts the conductor of the printed circuit board, is exposed.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: April 6, 2004
    Assignee: J.S.T. Mfg. Co., Ltd.
    Inventors: Taiji Hosaka, Masaaki Miyazawa
  • Patent number: 6717249
    Abstract: A non-contact type IC card includes an insulating film having first and second surfaces. A plane coil is arranged on the first surface of the film. A semiconductor element is arranged on the first surface of the film. The film has through holes which expose terminals of the plane coil and electrode terminals of the semiconductor element to the second surface of the film. A wiring pattern consisting of conductive paste is filled in the through holes and extends therebetween along the second surface of the film so that the terminals of the plane coil are electrically connected to the electrode terminals of the semiconductor element by means of the wiring pattern.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: April 6, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masatoshi Akagawa