Patents Examined by Joseph D Manoskey
  • Patent number: 11507443
    Abstract: Methods, systems, and apparatuses related to a memory fault map for an accelerated neural network. An artificial neural network can be accelerated by operating memory outside of the memory's baseline operating parameters. Doing so, however, often increases the amount of faulty data locations in the memory. Through creation and use of the disclosed fault map, however, artificial neural networks can be trained more quickly and using less bandwidth, which reduces the neural networks' sensitivity to these additional faulty data locations. Hardening a neural network to these memory faults allows the neural network to operate effectively even when using memory outside of that memory's baseline operating parameters.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Andrew Roberts
  • Patent number: 11500714
    Abstract: Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jay Sarkar, Cory Peterson
  • Patent number: 11487622
    Abstract: A system for package management includes an interface and a processor. The interface is to receive an indication to install a package. The processor is to determine a configured package using a set local configuration properties and using the package and to launch, using a metascheduler, a set of subschedulers to install a plurality of applications of the configured package.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 1, 2022
    Assignee: D2iQ, Inc.
    Inventors: Connor Patric Doyle, Thomas Rampelberg, Cody Maloney, José Armando García Sancio
  • Patent number: 11481264
    Abstract: A data processing apparatus includes a first processing unit that executes real-time processing with respect to data, a second processing unit that executes batch processing with respect to data that is output from the first processing unit as a result of processing by the first processing unit, and a monitor that monitors a status of the processing by the first processing unit and a status of processing by the second processing unit. The first processing unit includes a plurality of subprocessing units and buffers, and the second processing unit also includes a plurality of subprocessing units and buffers. The second processing unit includes a storage. The monitor includes a first monitor that monitors, for each of the buffers included in the first processing unit, an amount of the data stored in the corresponding buffer and a second monitor that monitors a total amount of the data stored in the buffers included in the second processing unit and the data stored in the storage.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 25, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Osamu Nasu, Jijun Jin, Ryo Kashiwagi
  • Patent number: 11481282
    Abstract: A method of fault-tolerant process control includes providing a network process control system in an industrial processing facility (IPF) including a plant-wide network coupling a server to computing platforms each including computing hardware and memory hosting a software application for simultaneously supporting a process controller and another process controller or an I/O gateway. The computing platforms are coupled together by a private path redundancy network for providing a hardware resource pool. At least some of the computing platforms are directly coupled by an I/O mesh network to a plurality of I/O devices to field devices that are coupled to processing equipment. Upon detecting at least one failing device in the hardware resource pool, over the private path redundancy network a backup is placed into service for the failing device from the another process controller or I/O gateway that is at another of the computing platforms in the hardware resource pool.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 25, 2022
    Assignee: Honeywell International Inc.
    Inventors: Paul Francis McLaughlin, Jason Thomas Urso, James Michael Schreder, John Rosa-Bian, Norman Swanson, Jethro F. Steinman
  • Patent number: 11481272
    Abstract: The present technology relates to an electronic device. A memory controller controls a memory device such that a life of the memory device is increased. The memory controller that controls the memory device includes a flash translation layer configured to generate a device health descriptor based on device information received from the memory device, and a bad block controller configured to generate a bad block table based on bad block information received from the memory device, and generate recycling information for recycling pages in bad blocks recorded in the bad block table based on the device health descriptor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventor: Ki Young Kim
  • Patent number: 11474888
    Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael R. Spica, Patrick T. Caraher
  • Patent number: 11474899
    Abstract: An open-channel storage device being configured to be controlled by a host including a bad block manager, the open-channel storage device including a buffer memory and a nonvolatile memory device. An operation method of the open-channel storage device includes performing a normal operation under control of the host, detecting a sudden power-off immediately after a program failure associated with a first data block among a plurality of memory blocks included in the nonvolatile memory device while the normal operation is performed, dumping a plurality of user data stored in the buffer memory to a dump block among the plurality of memory blocks in response to the detected sudden power-off, detecting a power-on, and performing a data recovery operation on the plurality of user data stored in the dump block in response to the detected power-on.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Kim, Jongwon Lee, Kyungwook Ye, Minseok Ko, Yangwoo Roh, Sung-Hyun Cho
  • Patent number: 11467896
    Abstract: Aspects pertaining to a crash dump file are described. In an example, the crash dump file may include one or more sections within which crash-related data is stored. A content file is also described which records valid parameters, wherein the valid section parameters pertain to corresponding sections within the crash dump file.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 11, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Prashant Anant Paranjape, Paul E Stolle, Sandhiya Krishnasamy
  • Patent number: 11461199
    Abstract: A redundancy method includes that a first disaster management function (DMF) device on a first site side receives a first request including identification information of a first virtual machine (VM) and a recovery point objective (RPO), allocates a maximum allowable delay time to each node that input/output (IO) data of the first VM passes through in a redundancy process, and sends a second request to a second DMF device on a second site side. The second request includes a maximum allowable delay time of a second replication gateway function (RGF) device on the second site side, and a maximum allowable delay time of an IO writer function (IOWF) device on the second site side and requests the second site side to perform redundancy on the first VM. Hence, the RPO requirements of the tenants can be satisfied in an entire redundancy process.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: October 4, 2022
    Assignee: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.
    Inventors: Xiangyang Wu, Zhi Zhao, Rong Chen, Xuan Jiang
  • Patent number: 11461160
    Abstract: A method and a device for a reaction-free and integrity-protected synchronization of log data between at least one first network and a second network is provided. The log data is copied by means of a monitoring device upon being transmitted from devices to a first log server in the first network. Metadata of the log data is additionally generated in a first managing unit, the metadata including time information, integrity information, origin information, and/or completeness information. The copied log data and the corresponding metadata are transmitted to the second network via a unidirectional coupling unit in a reaction-free manner. The lot data is checked and ordered chronologically in the second network using the metadata. Thus, a synchronized copy of the log data from the first network is promptly provided in the second network.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 4, 2022
    Inventors: Rainer Falk, Matthias Seifert, Martin Wimmer
  • Patent number: 11455218
    Abstract: A main memory includes unit memory regions, a redundancy memory region for replacing one or more of the unit memory regions, an address wrapper for generating an address increase/decrease control signal in first and second address wrapping modes, a column decoder for sequentially selecting memory cells in a faulty memory region where a fault has occurred, among the unit memory regions in the first address wrapping mode, and sequentially selecting redundancy memory cells in the redundancy memory region in the second address wrapping mode, based on a column address and the address increase/decrease control signal, and a data input/output circuit for outputting data read from the faulty memory region as backup data to a temporary memory in the first address wrapping mode, and outputting the backup data as restoration data to the redundancy memory region in the second address wrapping mode.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun-Ju Yoon
  • Patent number: 11449375
    Abstract: Rehabilitating storage devices in a storage array that includes a plurality of storage devices, including: receiving a request to rehabilitate a storage device that is operating outside of a defined range of expected operating parameters; selecting, from a hierarchy of rehabilitative actions that can be performed on the storage device, a rehabilitative action to perform on a storage device in dependence upon information describing a number of times that one or more of the rehabilitative actions have been performed on the storage device; and initiating execution of the selected rehabilitative action.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: September 20, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, James Cihla, Jungkeun Kim, Iris Mcleary, Damian Yurzola
  • Patent number: 11449397
    Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 20, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Glenn David Gilda, Thomas E. Miller, Arthur O'Neill
  • Patent number: 11442812
    Abstract: If processing of a first event in response to a stream event is not normally ended due to an occurrence of an exception or a timeout, the processing is executed repeatedly during a predetermined period of time from an occurrence of the first event. Then, after the predetermined period of time passes, an error notification is issued while processing of a second event that has occurred during the predetermined period of time is executed only once.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 13, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tetsu Imai
  • Patent number: 11436070
    Abstract: Embodiments are described for prioritizing input/output (I/O) operations dispatched from a storage media to a host bus adapter in a network, by tagging, in an I/O tagging module, the I/O operations in a file system supporting applications generating the I/O operations, wherein all child I/O operations initiated from a parent I/O operation are tagged with a same unique tag ID; tracking a time of arrival of each I/O operation of the I/O operations; and dispatching, in a transactional I/O scheduler, all sibling I/O's of the parent I/O operation based on a unique tag ID for the sibling I/Os, a respective time of arrival of each of the sibling I/Os, and defined quality of service (QoS) requirements.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rahul Ugale, Colin Zou
  • Patent number: 11436115
    Abstract: The present disclosure discloses a design and test method of a test plan. The test plan includes the plurality of input parameters, the plurality of output parameters, the plurality of system parameters, all of the numerical levels or the types of each input parameter, each output parameter and each system parameter. The test plan includes a plurality of test cases to cover combination conditions including a great number of the input parameters, the output parameters and the system parameters and their dynamic cross of the parameters. The design and test method performs the test cases of the test plan on the product automatically by considering overall possibly parameters and their levels associated with the product. The overall possibly parameters and their levels associated with the product can be tested before the product is dispatched to the customer so as to enhance the product quality.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 6, 2022
    Assignee: DELTA ELECTRONICS (THAILAND) PUBLIC COMPANY LIMITED
    Inventors: Chin Huat Lim, Ming-Li Shiu, Adisak Paepoot, Narut Udomchoke
  • Patent number: 11429466
    Abstract: A method and apparatus of performing fault tolerance in a fault tolerant computer system comprising: a primary node having a primary node processor; a secondary node having a secondary node processor, each node further comprising a respective memory; a respective checkpoint shim; each of the primary and secondary node further comprising: a respective non-virtual operating system (OS), the non-virtual OS comprising a respective; network driver; storage driver; and checkpoint engine; the method comprising the steps of: acting upon a request from a client by the respective OS of the primary and the secondary node, comparing the result obtained by the OS of the primary node and the secondary node by the network driver of the primary node for similarity, and if the comparison of indicates similarity less than a predetermined amount, the primary node network driver informs the primary node checkpoint engine to begin a checkpoint process.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: August 30, 2022
    Inventors: Charles J. Horvath, Lei Cao, Steven Michael Haid, John R. MacLeod, Angel L. Pagan, Nathaniel Horwitch Dailey, Wendy J. McNaughton, Stephen J. Wark
  • Patent number: 11416342
    Abstract: Embodiments for systems and methods of providing a boot order for containers in a cloud native application environment by collecting container environment data from a first container site; determining dependencies and connections between the containers and applications executed within the containers based on a number of system parameters; calculating a recommended order for booting or rebooting the containers during a disaster recovery process; and communicating the recommended order to a system administrator through a graphical user interface (GUI) for acceptance or modification by the system administrator.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 16, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: David Zlotnick, Assaf Natanzon, Boris Shpilyuck
  • Patent number: 11416375
    Abstract: The present disclosure describes methods, systems, and computer program products for providing additional stack trace information for time-based sampling (TBS) in asynchronous execution environments. One computer-implemented method includes determining whether time-based sampling is activated to capture a time-based sampling data during execution of a JavaScript function; in response to determining that the time-based sampling is activated to capture the time-based sampling data, determining whether a callback stack trace is active; in response to determining that the callback stack trace is active, loading the callback stack trace; retrieving a current stack trace of the JavaScript function; and saving the loaded callback stack trace and the current stack trace of the JavaScript function as the time-based sampling data.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: August 16, 2022
    Assignee: SAP SE
    Inventors: Ralf Schmelter, Rene Schuenemann, Axel Siebenborn