Patents Examined by Joseph D Manoskey
  • Patent number: 10445218
    Abstract: Methods and devices for testing graphics hardware may include reading content of a selected capture file from a plurality of capture files. The methods and devices may include transferring content from the selected capture file to an emulator memory of an emulator separate from the computer device. The methods and devices may include executing at least one pseudo central processing unit (pseudo CPU) operation to coordinate the execution of work on a graphics processing unit (GPU) of the emulator using the content from the selected capture file to test the GPU. The methods and devices may include receiving and store rendered image content from the emulator when the work is completed.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 15, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aaron Rodriguez Hernandez, Jason Gould, Cole Brooking, Nihar Mohapatra, Parikshit Gopal Narkhede, Veena K. Malwankar
  • Patent number: 10445197
    Abstract: Secondary nodes may detect failover operations for applications performing at a primary node. Application state indications may be collected at a primary node and reported to a monitor for the primary node. A secondary node may obtain the state indications from the monitor in order to evaluate whether the application is performing correctly at the primary and if not, trigger a failover operation to switch performance of the application to the secondary node. In some embodiments, the state information may be encoded into a single metric that can be obtained by the secondary node and evaluated to detect failover events.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 15, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Harpreet
  • Patent number: 10437702
    Abstract: The present invention is directed to a method for diagnosing faults in a software system, according to which, predictions of the probability of each software component of the software system to be faulty are obtained from a diagnoser, and the probability predictions are input to a fault diagnosis software module, executed by the diagnoser.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 8, 2019
    Assignee: B. G. Negev Technologies and Applications Ltd., at Ben-Gurion University
    Inventors: Meir Kalech, Ron Zvi Stern, Amir Elmishali
  • Patent number: 10437693
    Abstract: According to an embodiment of the present invention, an automated computer implemented method and system for implementing a network architecture comprising: a first co-location comprising: a first pod that supports a first subset of users; a second pod that support a second subset of user; a first failover pod that supports one or more other pods from a second co-location and one or more other pods from a third co-location during failover mode; the second co-location comprising: a third pod that supports a third subset of users; a fourth pod that supports a fourth subset of users; a second failover pod that supports one or more other pods at the first co-location and one or more pods from another co-location during failover mode; and an enterprise entity that replicates data for each of the co-locations and communicates the replicated data to the first co-location and the second co-location.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 8, 2019
    Assignee: JPMorgan Chase Bank, N.A.
    Inventors: Michael L. Lewis, Richard J. Romanelli
  • Patent number: 10430261
    Abstract: The subject matter described herein is generally directed towards detection and remediation of virtual computing instance (VCI) failure on host devices. Monitoring is performed to detect suspected failures of different guest operating systems, identify failure information, and perform remediation to provide high availability for the VCI.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: October 1, 2019
    Assignee: VMware, Inc.
    Inventors: Keith Farkas, Kevin Scott Christopher, Aalap Desai, Manoj Krishnan, Jesse Andrew Mendonca, Rohan Patil
  • Patent number: 10423522
    Abstract: A computer-implemented method of detecting a likely software malfunction is provided. The method comprises collecting a plurality of software error data sets wherein each software error data set comprises a proposed code section containing an error and a corrected code section containing code changes that fixed the error in the proposed code section. The method further comprises training a computer-implemented algorithmic model using the collected software error data sets to devise a software code classifier for predicting a likely error in a code section, reviewing a section of code using the software code classifier, and identifying suspicious code in the reviewed section of code as containing a suspected error using the software code classifier.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 24, 2019
    Assignee: salesforce.com, inc.
    Inventor: Philip Bergen
  • Patent number: 10417079
    Abstract: Embodiments of the present disclosure relate to a fault tolerant root cause analysis (RCA) system that is able to handle calculation failures during runtime. Calculations (e.g., evaluation of a diagnostic model for a specific component or device) that are performed during the RCA are integrated using different resources of the system under analysis. In order to make a final diagnosis, the resources exchange messages containing calculation inputs and outputs. Calculation problems due to calculation failures in a particular resource can be resolved efficiently which reduces resource utilization and minimizes failure propagation to other parts of the system. Accordingly, the system is able to recover and output a diagnosis even if some of the resources fail or generate problems.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 17, 2019
    Assignee: CA, Inc.
    Inventors: Michal Zasadzinski, Marc Sole Simo, Victor Muntes Mulero
  • Patent number: 10417106
    Abstract: A system includes a first software module, a storage module and a second software module. The first software module receives first data and analyzes the first data to obtain first processed data corresponding to the first data. The storage module stores the first processed data. The second software module receives second data and obtains values in first processed data corresponding to parameters of the second software module, and analyzes the obtained values and the second data to obtain second processed data.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 17, 2019
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) CO., LTD.
    Inventor: Shih-Cheng Wang
  • Patent number: 10402287
    Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Harvey Ray, Chris Michael Brueggen
  • Patent number: 10402248
    Abstract: A method and a program capable of controlling an error rate of device-specific information are provided.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 3, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yohei Hori, Kazukuni Kobara, Toshihiro Katashita, Toshihiro Matsui
  • Patent number: 10402261
    Abstract: An example device in accordance with an aspect of the present disclosure includes a redundancy controller and/or memory module to prevent data corruption and single point of failure in a fault-tolerant memory fabric. Devices include engines to issue and/or respond to primitive requests, identify failures and/or fault conditions, and receive and/or issue containment mode indications.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Harvey Ray
  • Patent number: 10402272
    Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the background records are for representing previous data operations, calculate a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism, and generate an adjusted step based on the trigger measure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Larry J. Koudele
  • Patent number: 10402273
    Abstract: The disclosed technology is generally directed to IoT device update failure recovery. In one example of the technology, after writing an updated release to memory, a determination is made whether the updated release is valid. The updated release includes a plurality of image binaries. If the updated release is determined to be valid, the updated release is made the current release. A determination is made as to whether the current release is stable. Upon determining that the current release is unstable, an auto-rollback is performed. Performing the auto-rollback includes, via at least one processor, automatically: obtaining an uncompressed backup of a previous release; making the uncompressed backup of the previous release the current release; and executing the uncompressed backup.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Reuben R. Olinsky, Edmund B. Nightingale
  • Patent number: 10379961
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by, receiving a write data object request and writing and committing the data object as a set of encoded data slices into DSN memory. The method continues by writing and committing an index consistency write-intent to DSN memory. The method continues by writing metadata of the data object to DSN memory. The method continues by write and committing an index entry to DSN memory. The method continues, during a finalization of the index consistency write-intent, by executing the index consistency write-intent to ensure consistency between the metadata of the data object and metadata located in the index entry.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Scholl, Jeremy S. Jarczyk, Wesley B. Leggette, Jason K. Resch, Yogesh R. Vedpathak, Manish Motwani, Tyler K. Reid
  • Patent number: 10379922
    Abstract: The present disclosure relates to error recovery in a virtual machine-based development environment. An example method generally includes monitoring for an error event in a virtual machine managed within a development environment. The development environment attempts to recover the virtual machine from the error event by performing a first error remediation procedure on the virtual machine. Upon determining that the first error remediation procedure failed to recover the virtual machine from the error event, the development environment attempts to recover the virtual machine from the error event by performing a second error remediation procedure on the virtual machine. The second remediation procedure may be a procedure that is more severe than the first error remediation procedure.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 13, 2019
    Assignee: INTUIT INC.
    Inventors: Chad Bell, Vinay Kumar, Ryan Lynch, Joseph Elwell
  • Patent number: 10380001
    Abstract: A process for determining a problematic condition while running software includes: loading a first pattern data set into a volatile memory of a computer, with the first pattern data set being associated with a set of problematic conditions, determining that a runtime symptom code generated while running software on the computer matches a pre-defined symptom code in a set of pre-defined symptom codes, collecting information during runtime according to a set of data collection instructions as a set of collected data, and determining, by applying a set of logic data to the set of collected data, a first problematic condition of the set of problematic conditions triggered the runtime symptom code.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anoop G. M. Ramachandra, Murali K. Surampalli
  • Patent number: 10380003
    Abstract: A diagnostic workflow file can be used to control the future diagnostic actions taken by a debugger without user interaction with the debugger when it executes. The diagnostic workflow file is used by a debugger during a debug session. The debugger performs the actions directed by the diagnostic workflow file to simulate an interactive live debug session. The diagnostic workflow file can include conditional diagnostic operations whose execution depends on the state of program variables, diagnostic variables and diagnostic primitives in the debug session.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 13, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jackson Davis
  • Patent number: 10372596
    Abstract: Aspects capture test coverage in a distributed system, wherein a processor instigates execution of a unique hypertext transfer request protocol test case within a distributed system of different, networked servers. The header of the unique test case includes a unique name for the unique test case, and the distributed system servers are each configured to, in response to processing a test case, generate a time-stamped log entry that includes header data for the processed test case and a uniform resource locator address of the processing server. The processor thus maps the unique test case to a subset of the distributed system servers as endpoint servers of the unique test case, in response to determining that the uniform resource locator addresses of each of the subset endpoint servers are listed within generated log entries of the endpoint servers in association with the unique test case name.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Adam G. Archer, Herman S. Badwal, Miran Badzak, Robin Y. Bobbitt, Mark T. Duquette, Christopher M. Lee-Shanok, Robert Retchless, Lauren H. Schaefer, Christopher N. Taylor
  • Patent number: 10372545
    Abstract: A microcontroller system includes a processing unit, a first peripheral having a first set of registers, and an assurance module. The first peripheral is configured to receive a first reset signal that resets the first set of registers to a first actual reset value, which is expected to be a first expected value. The assurance module is configured to calculate a first signature value, which is based on the first actual reset value, in response to the first reset signal. The processing unit is configured to perform a first comparison between the calculated first signature value and a pre-determined first signature value to determine whether the microcontroller system is in a trusted safety state. The first comparison is performed in response to the first reset signal, and the pre-determined first signature value is based on the first expected value.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies AG
    Inventors: Boyko Traykov, Veit Kleeberger, Rafael Zalman
  • Patent number: 10372563
    Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Young Sun Han