Abstract: A test apparatus for generating a test case based on a fault injection technique and a method of controlling the same are disclosed. The method includes identifying at least one function in a program to be tested based on a software detailed design, generating a test design document based on fault location that can be generated in connection with the identified at least one function and a fault type to be injected into the fault location, searching for the fault location to be injected based on the generated test design document and source code of the program, determining a fault injection scheme and the fault type, and predicting a result by applying a fault injection corresponding to the fault injection scheme and the fault type into the searched location to generate a test case.

Abstract: Disclosed are hardware and techniques for correcting computer process faults by identifying risk associated with correcting a computer process fault and computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a stream of process break flags from a monitoring component coupled to the network. Each computer process break flag in the stream of computer process break flags indicates a process fault detected by the monitoring component and is correlated to a corrective response. The break flag and the corrective response are assigned a risk. A risk matrix accounts for interdependencies between computer processes and identified corrective actions. A final response strategy that corrects the computer process faults is determined using the assigned risk and computer system interdependence.

Abstract: A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Abstract: The disclosed technology provides techniques, systems, and apparatus for containing and recovering from uncorrectable memory errors in distributed computing environment through migration of virtual machines and associated memory to a target host machine. An aspect of the disclosed technology includes a hypervisor or virtual machine manager that receives signaling of an uncorrectable memory error detected by a host machine. The virtual machine manager then uses information received via the signaling to identify virtual memory addresses or memory pages associated with the corrupted memory element so as to allow for containment and recovery from the error, and for live migration of the virtual machine.

Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.

Abstract: An encoder receives an application log file including component values and encodes the component values into lists of preliminary encoded values. The lists of preliminary encoded values are combined into a combined list of preliminary encoded values. An encoder-decoder neural network is trained to encode the combined list of preliminary encoded values into a list of collectively encoded values, to decode the list of collectively encoded values into a list of decoded values, and to optimize a metric measuring the encoder-decoder neural network's functioning, in response to receiving the combined list of preliminary encoded values. The trained encoder-decoder neural network receives combined lists of preliminary encoded values for application log files and encodes the combined lists of preliminary encoded values into lists of collectively encoded values.

Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.

Abstract: The disclosed technology provides techniques, systems, and apparatus for containing and recovering from uncorrectable memory errors in distributed computing environment. An aspect of the disclosed technology includes a hypervisor or virtual machine manager that receives signaling of an uncorrectable memory error detected by a host machine. The virtual machine manager then uses information received via the signaling to identify virtual memory addresses or memory pages associated with the corrupted memory element so as to allow for containment and recovery from the error.

Abstract: The present disclosure describes methods, systems, and computer program products for providing additional stack trace information for time-based sampling (TBS) in asynchronous execution environments. One computer-implemented method includes determining whether time-based sampling is activated to capture a time-based sampling data during execution of a JavaScript function; in response to determining that the time-based sampling is activated to capture the time-based sampling data, determining whether a callback stack trace is active; in response to determining that the callback stack trace is active, loading the callback stack trace; retrieving a current stack trace of the JavaScript function; and saving the loaded callback stack trace and the current stack trace of the JavaScript function as the time-based sampling data.

Abstract: Embodiments for simulating timing-related error conditions in a distributed system, by allowing a user to define a fault map specifying one or more faults to be committed by components in the distributed system. These generated fault events are to be executed in different components of the distributed system in a serialized distributed order. An event injection process delivers the fault map messages to the nodes in the distributed system, and the nodes then execute an operation sequence containing the fault events in the proper order as coordinated by the event injection process. The faults are then committed by the associated components in the nodes. Execution of these fault events occurs before, after or during a regular component procedure or action to simulate the desired timing-related error.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: To preserve error context during a reboot of a computing device, firmware within the computing device can be configured to implement a method that includes determining where the error context is stored in volatile memory. The method can also include identifying a plurality of recorder regions in non-volatile memory that have been assigned to store the error context. The plurality of recorder regions can be disaggregated across a plurality of distinct non-volatile memory regions. The method can also include flushing the error context from a plurality of different volatile memory locations to the plurality of recorder regions in response to detecting a trigger. The flushing can occur prior to the reboot of the computing device. The method can also include restoring at least some of the error context to the volatile memory after the computing device has been rebooted.

Abstract: Examples described herein generally relate to processing event logs where, for each of multiple events in an event log of the one or more event logs, a table of logged event instances can be generated for the event. For each of the multiple events, the table can be processed using an autoencoder to identify one or more of the logged event instances as anomalies, and an indication of at least a portion of the anomalies can be output. In addition, the event logs and/or corresponding tables of events can be used to train models for the autoencoders.

Abstract: Temporarily limiting access to a storage device, including: determining that a storage device of a plurality of storage devices in a storage system is operating outside of a defined performance range; determining that the storage device operating outside of the defined performance range may be caused by a rehabilitative action performed on the storage device; and modifying a storage operation issuance policy for one or more storage devices of the plurality of storage devices until a determination that the storage device is operating within the defined performance range.

Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

Abstract: Methods, systems, and apparatuses related to a memory fault map for an accelerated neural network. An artificial neural network can be accelerated by operating memory outside of the memory's baseline operating parameters. Doing so, however, often increases the amount of faulty data locations in the memory. Through creation and use of the disclosed fault map, however, artificial neural networks can be trained more quickly and using less bandwidth, which reduces the neural networks' sensitivity to these additional faulty data locations. Hardening a neural network to these memory faults allows the neural network to operate effectively even when using memory outside of that memory's baseline operating parameters.

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for autonomously adapting data storage system performance, lifetime, capacity and/or operational requirements. A data storage system may comprise a controller and one or more non-volatile memory devices. The controller is configured to determine a category for a workload of one or more operations being processed by the data storage system using a machine-learned model. The controller is configured to determine an expected degradation of the one or more non-volatile memory devices. The controller is configured to adjust, based on the expected degradation and an actual usage of physical storage of the data storage system by a host system, an amount of physical storage of the data storage system available to the host system.

Abstract: A system for package management includes an interface and a processor. The interface is to receive an indication to install a package. The processor is to determine a configured package using a set local configuration properties and using the package and to launch, using a metascheduler, a set of subschedulers to install a plurality of applications of the configured package.