Patents Examined by Joseph E. Clawson, Jr.
  • Patent number: 5652719
    Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: July 29, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoharu Tanaka, Gertjan Hemink
  • Patent number: 5650957
    Abstract: A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the present invention includes: a buried capacitor consisting of a storage electrode, a dielectric layer and a plate electrode formed on a substrate in a planar form; and a transistor formed above the capacitor, a source/drain region of the transistor being connected to the storage electrode of the capacitor.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: July 22, 1997
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Jong Moo Choi
  • Patent number: 5650960
    Abstract: A method for programming a memory cell is disclosed. The state of the memory cell is determined by the presence or absence of a spacer short. A memory cell has a floating gate, a control gate and an insulating layer separating the floating gate and the control gate. Spacers are deposited on the sides of the control gate and the insulating layer. When the cell is selected to be programmed in the "off" or non-conductive state, the spacers are in contact only with the control gate and the insulating layer. When the cell is selected to be programmed in the "on" or conductive state, the spacers are in contact with the control gate, the insulating layer, and the floating gate, thereby creating a spacer short.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: July 22, 1997
    Assignee: United Microelectronics Corporation
    Inventor: Peter Hsue
  • Patent number: 5640345
    Abstract: Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: June 17, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Okuda, Takashi Hori, Ichiro Nakao
  • Patent number: 5640346
    Abstract: An EPROM cell comprises an MOS device including a floating gate electrode overlying, and ohmically insulated from, the channel region of the MOS device, and a separate diode including a p-n junction having a substrate surface intercept. A floating gate electrode overlies the diode p-n junction intercept and is ohmically isolated therefrom by an intervening insulating layer. Writing of data into the floating gate electrode of the MOS device is achieved by causing a voltage breakdown across the diode p-n junction and the flow of high energy electrons across the junction. A voltage is simultaneously applied to the diode gate electrode thereby attracting some of the high energy electrons through the overlying insulating layer into the diode floating gate electrode. The diode gate electrode is ohmically connected to the MOS floating gate electrode on which some of the electrons are stored for affecting the turn-on, turn-off characteristics of the MOS device.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: June 17, 1997
    Assignee: Harris Corporation
    Inventor: Donald Ray Preslar
  • Patent number: 5640360
    Abstract: An address buffer circuit for a semiconductor memory device includes first and second address inputs which are selectably connectable to a first node according to first and second address input control signals, respectively. The device also includes first and second switches which are controlled by a refresh mode signal and selectively output a first or second address enable signal. Further, a latch is provided which latches the address signal input to the first node, and outputs the latched address signal in periods of the selected first or second address enable signals.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: June 17, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hong Kim, Jin-Man Han, Hyung-Dong Kim
  • Patent number: 5638320
    Abstract: Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read process determines a memory cell's threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts. Another read process slowly ramps the source voltage of a memory cell and determines the cell's threshold voltage from the drain voltage of the memory cell. Still another read process connects a cascoding device to a memory cell and biases the memory cell in the linear region while the threshold voltage of the memory cell is determined from a voltage across a load which carries a current that mirrors the current through the memory cell. Read processes disclosed for analog memory cells also apply to binary memory cells, multilevel digital memory cells, and other applications which require precise reading of threshold voltages.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: June 10, 1997
    Assignee: inVoice Technology, Inc.
    Inventors: Sau C. Wong, Hock C. So
  • Patent number: 5636162
    Abstract: A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: June 3, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Tim M. Coffman, Sung-Wei Lin, Phat C. Truong
  • Patent number: 5633829
    Abstract: A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: May 27, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Matsumura, Masahiko Yoshimoto
  • Patent number: 5629891
    Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: May 13, 1997
    Assignee: Synaptics, Incorporated
    Inventors: John LeMoncheck, Timothy P. Allen, Gunter Steinbach, Carver A. Mead
  • Patent number: 5627778
    Abstract: A memory sensing scheme is disclosed which does not require the use of a dummy cell. The memory sensing scheme uses charge injection and parasitic capacitive coupling to distinguish the logical content of a memory cell.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: May 6, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Hiep V. Tran
  • Patent number: 5625593
    Abstract: A conventional memory card circuit has a construction where an input terminal and an output terminal of storage means are directly connected with a terminal unit. In consequence, the conventional memory card circuit has a disadvantage that the stored content of the storage means might be damaged when a signal applied from the terminal unit is unstable at the time of inserting or detaching a memory card into or from the terminal unit. Therefore, according to the present invention, a buffer is provided in each of input and output terminals of storage means and the storage means is cut off from outside by the buffer at the time of inserting or detaching a memory card into or from a terminal unit, whereby the stored content of the storage means can be prevented from being damaged.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: April 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masatoshi Kimura
  • Patent number: 5623443
    Abstract: An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: April 22, 1997
    Assignee: Waferscale Integration, Inc.
    Inventors: Reza Kazerounian, Rustom F. Irani, Boaz Eitan
  • Patent number: 5621696
    Abstract: Multiple reads are made from an array of single-read port memory cells. An array of single-read port memory cells is provided with "steering" devices located between a column of cells and the output drivers for the array. The steering devices are controlled by the read pointers such that the steering signal for a given output configuration is active only when read pointers for that output configuration are active. To complete the function, the read pointers are fed to OR gates, one per row, so that a given pointer will activate the read port of a plurality of consecutive memory cells. The read pointers represent the decoded read address and only one is active at a time.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: April 15, 1997
    Assignee: IBM Corporation
    Inventors: Sang H. Dhong, Joseph J. Nocera, Jr.
  • Patent number: 5619450
    Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: April 8, 1997
    Assignee: Fujitsu Limited
    Inventor: Tetsuji Takeguchi
  • Patent number: 5617351
    Abstract: A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: Claude L. Bertin, Donelli J. DiMaria, Makoto Miyakawa, Yoshinori Sakaue
  • Patent number: 5617356
    Abstract: A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: April 1, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Carla Golla, Silvia Padoan, Marco Olivo
  • Patent number: 5615153
    Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: March 25, 1997
    Inventors: Tom D. Yiu, Ray L. Wan, Ling-Wen Hsiao, Tien-Ler Lin, Fuchia Shone
  • Patent number: 5615152
    Abstract: The present invention provides a contactless flash EPROM array formed in a P-well in a diffused silicon substrate of N-type conductivity. To facilitate a channel erase operation, thin tunnel oxide is formed between the P-well and the overlying polysilicon floating gate EPROM cells. The array is programmed in a conventional EPROM cell array manner. However, in accordance with the invention, the channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row and holding the substrate at the supply voltage.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: March 25, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Albert Bergemont
  • Patent number: 5612912
    Abstract: In a multi-level DRAM, one of multiple voltage levels may be stored in each memory cell. In a four-level system, each of a pair of bitlines is divided into two subbitlines which are connected to respective sense amplifiers. Dummy cells matching the storage cell are provided on each subbitline to balance the capacitances of the subbitlines. The stored voltage is dumped onto left and right subbitlines which are then isolated, and one of the voltages is then sensed to provide a sign bit. A second reference level is generated by dumping the charge associated with the sign bit over three subbitlines and the magnitude bit is sensed using that reference. The stored voltage is restored by charge sharing a sign bit charge on two bitlines with a magnitude bit charge on one bitline.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: March 18, 1997
    Assignee: Mosaid Technologies Incorporated
    Inventor: Peter B. Gillingham