Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: A floating gate type field effect transistor increases the threshold during an application of a write-in pulse to the control gate electrode thereof so as to inject hot electrons into the floating gate electrode, and the write-in pulse is decayed along a waveform having a gradient smaller than a gradient of a pulse signal assumed to take place in a source/drain region of a non-selected floating gate type field effect transistor sharing the selected word line with the selected floating gate type field effect transistor, thereby preventing the non-selected floating gate type field effect transistor from the gate disturb phenomenon.

Abstract: A nonvolatile memory having a simple structure where recorded information can be read nondestructively. A voltage is applied between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the polarization of the applied voltage. A control gate voltage, necessary to form a channel, is small when the ferroelectric layer is polarized with the control gate side negative (polarized with second polarization). The control gate voltage V.sub.cg necessary to form a channel is large when the ferroelectric layer is polarized with the control gate side positive (polarized with first polarization). The reference voltage is applied to the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with the second polarization and a small drain current flows when the ferroelectric layer is polarized with the first polarization. Recorded information can be read by detecting the drain current.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator.

Abstract: A column selection circuit of a semiconductor memory includes a plurality of transfer gates each of which is arranged between each sense amplifier and each column select gate for gating each column to an internal bus according to a difference between a potential of each bit line and a precharge potential of each data bus.

Abstract: A thin film transistor (TFT) load type static random access memory (SRAM) which includes a memory capacitor in addition to the stray capacitance. The SRAM includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes first and second transfer transistors, first and second driver transistors, first and second thin film transistor loads and first and second memory capacitors. The first and second memory capacitors include a storage electrode, a dielectric layer which covers the storage electrode, and an opposing electrode formed on the dielectric layer. A connection region is provided in which the storage electrode of the first memory capacitor, the drain region of the second thin film transistor load and the gate electrode of the first driver transistor are connected.

Abstract: A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V.sub.pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V.sub.CC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.

Abstract: A semiconductor memory circuit comprises bit line pairs each of which has a pair of bit lines which are coupled to memory cells and have a first end portion and a second end portion, a pair of data bus lines, sense amplifiers each of which is coupled to a corresponding bit line pair, switching circuits each of which is coupled between the first end portion of the corresponding bit line pair and the data bus lines, each of the switching circuits connecting the bit line of the corresponding bit line pair and one of the data bus lines in response to a control signal, voltage difference detecting circuits each of which is coupled to the second end portion of the corresponding bit line pair, each of the voltage difference detecting circuits generating a detection signal when the bit lines of the corresponding bit line pair have different voltage potentials from each other, and a decoding circuit generating the control signals in response to address signals and the detection signal so that the corresponding bit lin

Abstract: A non-volatile semiconductor memory device, includes a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, the semiconductor layer and the ferroelectric layer forming a semiconductor-ferroelectric junction, a writing circuit in which a voltage higher than a coercive electric field of the ferroelectric material is applied to the capacitor of the memory cell to align a polarization direction of the ferroelectric layer in a predetermined direction so as to set a capacitance of the capacitor at a predetermined value, thereby writing data corresponding to the predetermined value of the capacitance, and a reading circuit in which a voltage less than the coercive electric field of the ferroelectric layer is applied to the capacitor of the memory cell in which the data is written, thereby reading the data.

Abstract: A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state.

Abstract: A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors.

Abstract: A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Abstract: SEU immunity is provided in a cross-coupled CMOS latch circuit by inserting a pair of series connected invertors between the drain node of one CMOS invertor and the gate node of the other CMOS invertor and a pair of series connected invertors between the drain node of the other CMOS invertor and the gate node of the one CMOS invertor. The invertor pairs delay the propagation of a change in voltage induced by an energetic ion strike at the off drain of one invertor to the gates of the transistors making up the other cross coupled invertor. The invertor connected to the gates of the transistors affected by the ion strike help in restoring the circuit to its original state.

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A tunnel insulating film is formed on a main surface of a silicon substrate. A floating gate electrode is formed on the tunnel insulating film. A nitride layer formed of a material of the floating gate electrode is formed in the vicinity of an interface between the floating gate electrode and the tunnel insulating film located in a tunnel region A. Therefore, the write/erase characteristics of a non-volatile semiconductor memory device can be improved without decreasing the driving capability of a memory transistor at lower voltages.

Abstract: A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.

Abstract: A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed.

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).