Patents Examined by Joseph E. Palys
  • Patent number: 6052744
    Abstract: A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: April 18, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Michael P. Moriarty, Thanh T. Tran, Thomas J. Bonola
  • Patent number: 6052800
    Abstract: A system for monitoring a computer system with an external status monitor during the power-on self test (POST) of the computer system. The computer system has tasks to be performed during the POST process. Each task has a token corresponding to an original message or a subsequently added message. Each subsequently added message is stored in the computer system, and each original message is stored in the external status monitor. Under the control of the computer system, the system identifies a task for the computer system to perform. The system then retrieves the token for the identified task and determines whether the retrieved token corresponds to an original message or a subsequently added message. If the retrieved token corresponds to an original message, the system sends only the retrieved token to the external status monitor.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: April 18, 2000
    Assignee: Micron Electronics, Inc.
    Inventors: Robert Gentile, Eric D. Anderson
  • Patent number: 6049887
    Abstract: A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: April 11, 2000
    Assignee: Intel Corporation
    Inventors: Narendra Khandekar, Ashish S. Gadagkar, Robert F. Kubick, Vincent E. VonBokern, Manish Muthal
  • Patent number: 6044418
    Abstract: A system and method for dynamically resizing queues used in a network switch to accommodate potential congestion situations without experiencing data loss. In one embodiment, partition pointer registers are used to indicate when resizing is desirable. The control logic then determines when it is safe to update the size of the queue such that no data loss occurs and timely updates the queue size.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 28, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Shimon Muller
  • Patent number: 6044478
    Abstract: A cache has programmable, finely ganular, locked-down regions within a way or way(s) so that the contents of the locked-down regions are not evicted. The finely granular locked-down regions need not be contiguous and are programmed as either "locked-valid" or "locked-invalid" to provide general purpose memory that is local and private to the processor or for masking defected cache lines or portions thereof. Finely granular, programmable spatial regions of the cache that are locked-down are preferably, although not exclusively, programmed through two additional states to the standard MESI (Modified, Exclusive, Shared, Invalid) protocol for multipurpose cache coherency.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: March 28, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Daniel W. Green
  • Patent number: 6044470
    Abstract: Password identification information for identifying a password for key verification is set for each of a plurality of applications. A current password storage unit for storing a password which has recently been input and the password identification information of the password is arranged. When one application is selected, password identification information corresponding to the application is verified with the password identification information stored in the current password storage unit. If the two password identification information match, key verification is performed using the password in the current password storage unit. With this operation, a plurality of data can be read out by performing the password input operation once. One or two select keys are arranged in place of a ten-key pad. By repeating an operation using the select keys and the enter key, a password having a plurality of digits is input. Therefore, the password can be input using a minimum number of keys.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: March 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryouichi Kuriyama
  • Patent number: 6041373
    Abstract: A kit in accordance with the invention is disclosed that allows for simultaneous connectivity of a variety of SCSI devices to a SCSI card via a SCSI bus. Such SCSI devices include internal narrow, internal wide, external narrow, and external wide devices. A kit in accordance with the invention includes a terminator-adapter. The terminator-adapter includes a first wide connector, a second narrow connector, and a wide bus including an upper and lower bus. The upper bus is coupled to the wide connector and is first and second connector as well as a soft terminator. By enabling the soft terminator, the terminator-adapter behaves as a wide bus terminator. By disabling the soft terminator, the terminator-adapter behaves as a wide-to-narrow adapter. A kit in accordance with the invention may further include a wide cable and a SCSI card. In various embodiments, the SCSI card includes a wide internal connector and a narrow internal connector.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: March 21, 2000
    Assignee: Diamond Multimedia Systems, Inc.
    Inventor: Duc Pham
  • Patent number: 6041417
    Abstract: The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 21, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Maynard D. Hammond, James M. Dewey
  • Patent number: 6041413
    Abstract: A computer system power-on security control apparatus is disclosed to provide shielding against unauthorized access to the computer systems. Firmware-level protection is provided instead of the conventional implementation at the operating system level. Repeated power-on and -off cycles inevitable in the process of trial entry of the password of the computer system can be avoided altogether, reducing the risk of potential damages to delicate subsystems in the computer while repeated trial of the password is attempted.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: March 21, 2000
    Assignee: Winbond Electronics Corp.
    Inventor: Cheng-Chih Wang
  • Patent number: 6041407
    Abstract: A system for sub-allocating space within a logical block in a disk-based file system is described. Each disk block is subdivided into an integer number of smaller sub-blocks. One or more of the sub-blocks may contain data samples. Associated with each block is a variable which indicates which sub-block within the block contains data which have been read from disk to memory. When an application performs a read operation, the variable is first checked to determine whether the data sample to be read is already in memory. If the data sample is in memory, no disk read operation for that data is required.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: March 21, 2000
    Assignees: Sony Corporation, Sony Pictures Entertainment, Inc.
    Inventors: Jeffrey Mark Claar, Roger Mather Duvall, Richard Joseph Oliver
  • Patent number: 6035423
    Abstract: A method for updating antivirus files on a computer using push technology is disclosed. In a preferred embodiment, updated virus signature files or other updated antivirus information is loaded onto a central antivirus server, while local push agent software is installed on the client computer. When the user of the client computer is connected to the Internet, the push agent software operates in the background to receive updated antivirus files from the central antivirus sever across the Internet, in a manner which is substantially transparent to the user. In another preferred embodiment, antivirus files on a plurality of client computers on a corporate computer network are automatically updated using push technology and automated network installation scripts. A service computer associated with the plurality of client computers receives one or batches of antivirus updates from a central antivirus server across the Internet using push technology.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: March 7, 2000
    Assignee: Network Associates, Inc.
    Inventors: Vernon Hodges, Shawn O'Donnell
  • Patent number: 6035403
    Abstract: A method is provided for protecting distributed software, either through the internet/telephone networks or via physical storage media like floppy diskettes, magnetic tapes, CD-ROMS, DVD-ROMS, etc., by using biometric information (personal fingerprint information in particular). In one approach, the fingerprint of the software purchaser is embedded into the purchased software at the time of purchase. All subsequent use of the software by the purchaser at his/her home or office is subject to (a) providing his/her fingerprint again and (b) the fingerprint matches that embedded in the purchased software. In another related approach, prior to the use or installation of distributed software, the user's computer calls a central management server station. The software then requests the user to provide his or her fingerprint by any device that would capture such information.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: March 7, 2000
    Assignee: HUSH, Inc.
    Inventors: Subramanian Subbiah, Yang Li, D. Ramesh K. Rao
  • Patent number: 6033441
    Abstract: A transfer of data between the first clock domain to the second clock domain is synchronized in a situation in which the first clock signal in the first clock domain is generated from a source independent from the second clock signal in the second clock domain. The ratio of one frequency to another is determined along with the phase relationship between the two clock signals during a selected period of time. Then, the phase relationship is predicted for a future period of time. This prediction of the relationship between the two clock signals serves as an input to a control mechanism, which prevents sampling of data and control signals when they are transitioned from one state to another.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: March 7, 2000
    Assignee: LSI Logic Corporation
    Inventor: Brian K. Herbert
  • Patent number: 6032168
    Abstract: In a parallel computer system having N parallel computing units a data pipeline connects all the computing units. In addition the computing units are coupled to a random access memory so that each computing unit is assigned to one column of the memory array. To perform a digital signal processing filter operation the required coefficients are stored in the memory so that one or more different filter operations can be carried out in an interleaved way.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: February 29, 2000
    Assignee: Motorola, Inc.
    Inventors: Yaron Ben-Arie, Effi Orian, Itzhak Barak, Jacob Kirschenbaum, Doron Kolton, Shay-Ping Thomas Wang, Shao-Wei Pan, Stephen-Chih-Hung Ma
  • Patent number: 6029256
    Abstract: A system and method for allowing computer programs to directly access various features of a virus scanning engine is disclosed. In one embodiment of the invention, the system includes a module for instantiating an object to act as an interface between the computer program and the virus scan engine, a module for setting properties of the object that are associated with the desired feature of the virus scan engine to be accessed, a module for invoking a method of the object, the invocation resulting in access to the desired feature of the virus scan engine, and a module for examining properties of the object after the desired feature of the virus scan engine has been accessed.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: February 22, 2000
    Assignee: Network Associates, Inc.
    Inventor: Viktor Kouznetsov
  • Patent number: 6029255
    Abstract: When an I/O request block is received from a file system, a number-of-system's-failures setting section stores the present number of failures in the I/O request block, and hands over the I/O request block to a software driver after taking a checkpoint. When the I/O request block is received from the software driver, a number-of-failures determining section determines whether or not the number of failures stored in the I/O request block coincides with the present number of failures. If they do not coincide, an I/O request error return section will return the I/O request block to the software driver without handing over it to a device driver and causes an I/O request completion processing section to reissue the I/O request block again.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: February 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kunio Yamada
  • Patent number: 6029183
    Abstract: A computer system is disclosed having two structures, a mobile core unit and an enclosure capable of enclosing and cooperating with the core unit. The core unit has all of the components of a general purpose computer except for a display and source of power. This core unit by itself is non-functional as a computer unless it is in electrical contact with the enclosure. The enclosure has several connector ports for attachment of peripherals to the system.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: February 22, 2000
    Assignee: Xybernaut Corporation
    Inventors: Michael D. Jenkins, John F. Moynahan
  • Patent number: 6026497
    Abstract: A system for facilitating determination of accurate timing of execution of a computer program fragment by a digital computer comprises a clock resolution determination subsystem and an iteration number determination subsystem. The clock resolution determination subsystem determines a clock resolution value representing a resolution of a clock provided by the digital computer. The iteration number determination subsystem uses the clock resolution value, and maximum and minimum desired time interval values, to determine an iteration number value, the iteration number representing a number of iterations for execution of the computer program fragment to provide accurate timing of the computer program fragment by the digital computer.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: February 15, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Mathew J. Myszewski
  • Patent number: 6026503
    Abstract: A device and method for interactively debugging a system controlled by a microprocessor. The device continuously monitors the signals passed along the system bus, watching for signals that match interactively defined break conditions and trace conditions. When a breakpoint condition is satisfied, the device causes the system's microprocessor to execute debug code, which either may mediate interactive control of the system by the user or may initiate the execution of a software patch. When a trace condition is satisfied, the device initiates tracing of bus activity. The device is controlled by the user using conventional interactive interface means such as a video terminal or a personal computer.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: February 15, 2000
    Assignee: Telrad Communication and Electronic Industries Ltd.
    Inventors: Simcha Gutgold, Menachem Honig, Vitaly Rubinovich, Ron Treves, Matias Veisman, Michael Wohlfarth
  • Patent number: 6016555
    Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: January 18, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas E. Deao, Natarajan Seshan