Patents Examined by Joseph Galvin, III
  • Patent number: 10276734
    Abstract: The present invention relates to plasmonic components, more particularly plasmonic waveguides, and to plasmonic photodetectors that can be used in the field of microoptics and nanooptics, more particularly in highly integrated optical communications systems in the infrared range (IR range) as well as in power engineering, e.g. photovoltaics in the visible range. The present invention also specifies a method for producing a plasmonic component, more particularly for photodetection on the basis of internal photoemission.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 30, 2019
    Assignee: Karlsruher Institut Für Technologie
    Inventors: Sascha Mühlbrandt, Jürg Leuthold, Manfred Kohl
  • Patent number: 10269976
    Abstract: To provide a transistor in which a channel is formed in an oxide semiconductor and which has stable electrical characteristics. To suppress shift in threshold voltage of a transistor in which a channel is formed in an oxide semiconductor. To provide a normally-off switching element having a positive threshold voltage as an n-channel transistor in which a channel is formed in an oxide semiconductor. A base insulating layer is formed over a substrate, an oxide semiconductor layer is formed over the base insulating layer, a first gate insulating layer is formed over the oxide semiconductor layer, a second gate insulating layer is formed over the first gate insulating layer by a sputtering method or an atomic layer deposition method at a substrate temperature of higher than or equal to 100° C., and a gate electrode layer is formed over the second gate insulating layer.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10269927
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a core region of a substrate and a plurality of second fin structures in a peripheral region of the substrate, forming a first dummy gate structure including a first dummy gate oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second gate oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate electrode layer, performing an ion implantation process to tune the threshold voltages of the first fin structures, and removing each first dummy gate oxide layer. The method also includes removing each second dummy gate electrode layer, and forming a gate dielectric layer and a metal layer on each first fin structure and each second fin structure.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10269962
    Abstract: A semiconductor device has a fin-type structure which extends in a first direction and includes a laminate of oxide and semiconductor patterns disposed one on another on a first region of a substrate, and a first gate electrode that extends longitudinally in a second direction different from the first direction on the fin-type structure. Each oxide pattern is an oxidized compound containing a first element.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Ryul Lee, Sang Moon Lee, Chul Kim, Ji Eon Yoon
  • Patent number: 10270002
    Abstract: The present disclosure relates to an integrated light emitting device. The integrated light emitting device comprises a substrate of semiconductor material, a light emitting unit integrated into the semiconductor material, and at least one cavity formed into the semiconductor material between the substrate and the light emitting unit. At least portions of the at least one cavity may be formed by Silicon-On-Nothing (SON) process steps.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Thoralf Kautzsch
  • Patent number: 10263008
    Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Nishida, Katsuyuki Sekine, Hirokazu Ishigaki, Yasuhiro Shimura
  • Patent number: 10243081
    Abstract: A highly reliable semiconductor device including a transistor using an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a first insulating layer is formed in contact with the oxide semiconductor layer, and an oxygen doping treatment is performed thereon, whereby the first insulating layer is made to contain oxygen in excess of the stoichiometric composition. The formation of the second insulating layer over the first insulating layer enables excess oxygen included in the first insulating layer to be supplied efficiently to the oxide semiconductor layer. Accordingly, the highly reliable semiconductor device with stable electric characteristics can be provided.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Terumasa Ikeyama, Katsuaki Tochibayashi
  • Patent number: 10243121
    Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that allow improved reliability under high current operation.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 26, 2019
    Assignee: Cree, Inc.
    Inventors: Bradley E Williams, Kevin W Haberern, Bennett D Langsdorf, Manuel L Breva
  • Patent number: 10243064
    Abstract: To provide a highly reliable semiconductor device by giving stable electrical characteristics to a transistor including an oxide semiconductor film. A gate electrode layer is formed over a substrate, a gate insulating film is formed over the gate electrode layer, an oxide semiconductor film is formed over the gate insulating film, a conductive film is formed over the oxide semiconductor film, so that a region in vicinity of an interface with the oxide semiconductor film in contact with the conductive film is made amorphous, heat treatment is performed, the conductive film is then processed to form a source electrode layer and a drain electrode layer, and a part of the amorphous region in the oxide semiconductor film which is exposed by formation of the source electrode layer and the drain electrode layer is removed.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10229912
    Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 12, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Taku Sato, Kazuya Uryu, Kazuyuki Shouji
  • Patent number: 10229878
    Abstract: A semiconductor device includes an insulating film formed to cover an electric fuse (EF1), an insulating film (IL1), an insulating film (IL2), an electric fuse (EF1), an insulating film (IL1), and an insulating film (IL2). The electric fuse (EF1) includes a fuse-blowing portion (FC1), a first pad portion (PD1), and a second pad portion (PD2). The fuse-blowing portion (FC1) is formed between the first pad portion (PD1) and the second pad portion (PD2) in a first direction and is a rectangular shape having a first short side and a second short side along a second direction perpendicular to the first direction. The insulating film (IL1) is formed continuously between the first short side and the second short side to cover the surface of the fuse-blowing portion (FC1). The insulating film (IL2) is formed to planarly surround the insulating film (IL1) and is arranged at an interval from the insulating film (IL1).
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: March 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihiro Nomura
  • Patent number: 10229950
    Abstract: An image sensor includes a substrate including a first surface and a second surface, a first device isolation layer disposed in the substrate and defining a plurality of pixels in the substrate, and having a lower surface adjacent the first surface of the substrate and an upper surface adjacent the second surface of the substrate. Each of the pixels includes a photoelectric conversion element, a floating diffusion region adjacent the first surface of the substrate, and a grid pattern on the second surface of the substrate. At least one of the grid patterns is not vertically aligned with the first device isolation layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun Ki Lee, Joonkyoung Lee
  • Patent number: 10217950
    Abstract: A stretchable film includes a first region including a plurality of first patterns having a concave polygonal shape. The stretchable film also includes a second region including a plurality of second patterns having a concave polygonal shape. The stretchable film further includes a buffer region between the first region and the second region.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 26, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Jin Joo, Won-Il Choi, Jong-Ho Hong
  • Patent number: 10217822
    Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Paul A. Nygaard, Stuart B Molin, Michael A Stuber, Max Aubain
  • Patent number: 10216028
    Abstract: The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, belongs to a field of black-matrix-less display technology, and can solve problems that a conductive reflecting structure in a display panel of prior art affects display effect and external visibility. The array substrate of the present invention comprises a conductive reflecting structure and metal particles provided above the conductive reflecting structure.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Seungjin Choi
  • Patent number: 10217918
    Abstract: A light-emitting element package according to an embodiment comprises: a substrate; a conductive layer arranged on the substrate; at least one light-emitting chip arranged on the substrate; a wire for electrically connecting the conductive layer and the at least one light-emitting chip; a wavelength conversion unit arranged on the light-emitting chip; and a molding unit arranged on the substrate so as to enclose the light-emitting chip and the wire and to expose the upper surface of the wavelength conversion unit, wherein the distance from the upper surface of the light-emitting chip to the upper surface of the wavelength conversion unit is larger than a value obtained by adding 37 ?m to the distance from the upper surface of the light-emitting chip to the highest point of the wire.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 26, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Gun Kyo Lee, Kwang Hee Lee
  • Patent number: 10205029
    Abstract: A TFT, a manufacturing method thereof, and a display device are provided. The TFT includes a semiconductor layer and an etch-stop layer merely covering a channel region of the semiconductor layer. The semiconductor layer and the etch-stop layer are formed through a single patterning process.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiushi Wang, Dalin Cui
  • Patent number: 10204933
    Abstract: The application provides a thin film transistor, a method for manufacturing the thin film transistor, and a display panel, the thin film transistor includes a metal electrode, and a step of forming the metal electrode includes: forming a first material layer on a substrate; performing a pattering process on the first material layer to form a groove pattern in the first material layer such that the groove pattern matches with a pattern of the metal electrode to be formed; forming the metal electrode in the groove pattern such that a gap is formed between an edge of the metal electrode and an edge of the groove pattern; forming a protection pattern on the substrate formed with the metal electrode such that the protection pattern covers the metal electrode and its edge. In the application, the protection pattern is formed on the resultant metal electrode and can effectively protect conductive metal.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongda Sun, Youngsuk Song, Jingang Fang
  • Patent number: 10199299
    Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes placing a sheet mold compound in a containment area defined by a tray cover, and dispensing a granular mold compound over the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed grains to a molding machine without using a release film.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kean Tat Koh, Lien Wah Choong
  • Patent number: 10199259
    Abstract: In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Michael Zier