Abstract: Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular embodiment includes placing a sheet mold compound in a containment area defined by a tray cover, and dispensing a granular mold compound over the sheet mold compound. The sheet mold compound can have a first density and the overall granular mold compound can have a second density less than the first density. The method further comprises transferring the solid sheet carrying the dispensed grains to a molding machine without using a release film.

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract: A seed crystal layer is provided on a supporting body. A laser light is irradiated from a side of the supporting body to provide an altered portion along an interface between the supporting body and seed crystal layer. The altered layer is composed of a nitride of a group 13 element and has a portion into which dislocation defects are introduced or an amorphous portion.

Abstract: An pixel unit includes a photoelectric conversion element, a transfer transistor having a transfer gate abutting on the photoelectric conversion element, and a floating diffusion region on which the transfer gate abuts, wherein the transfer gate includes a first gate portion having a first gate width in a gate width direction, the first gate portion abutting on the floating diffusion region and extending away from the floating diffusion region in a gate length direction, and a second gate portion having a second gate width narrower than the first gate width in the gate width direction, the second gate portion extending continuously from the first gate portion in the gate length direction, and wherein a width of the second gate portion gradually decreases from the first gate width to the second gate width toward a direction away from the first gate portion.

Abstract: Described herein are LED chips incorporating self-aligned floating mirror layers that can be configured with contact vias. These mirror layers can be utilized to reduce dim areas seen around the contact vias due to underlying material layers without the need for the mirror layer to be designed at some tolerance distance from the electrical via. This increases mirror area, eliminating lower light reflection in the proximity of the via and producing higher light output with greater light emission uniformity. In some embodiments, the mirror layer is formed with a contact via. This allows for a self-aligning process and results in the mirror layer extending substantially from the edge of the via.

Abstract: A photoelectric conversion element includes a buffer layer, a BSF layer, a base layer, a photoelectric conversion layer, an emitter layer, a window layer, a contact layer, and a p-type electrode sequentially on one surface of a substrate, and includes an n-type electrode on the other surface of the substrate. The photoelectric conversion layer has at least one quantum dot layer. The at least one quantum dot layer includes a quantum dot and a barrier layer. A photoelectric conversion member including the buffer layer, the BSF layer, the base layer, the photoelectric conversion layer, the emitter layer, the window layer, and the contact layer has an edge of incidence that receives light in an oblique direction relative to the growth direction of the quantum dot. A concentrator concentrates sunlight and causes the concentrated sunlight to enter the photoelectric conversion member from the edge of incidence.

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

Abstract: A thin film transistor, a method for fabricating the same, a display substrate, and a display device are disclosed. The method comprises: forming in sequence a light shielding layer, an insulating layer, and a semiconductor layer; and forming a pattern of the light shielding layer, the insulating layer, and the semiconductor layer in one patterning process. A polycrystalline silicon layer can be formed into an active layer and an amorphous silicon layer into the light shielding layer, by using only one mask. The number of masking processes is reduced by one, which simplifies a fabricating process of the thin film transistor.

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

Abstract: A UV light emitting device includes: an n-type contact layer including an AlGaN layer or an AlInGaN layer; a p-type contact layer including a AlGaN layer or an AlInGaN layer; and an active layer of a multi-quantum well structure placed between the n-type contact layer and the p-type contact layer. The active area of the multi-quantum well structure includes barrier layers and well layers. The well layers include electrons and holes present according to probability distributions thereof. The barrier layers are formed of AlInGaN or AlGaN and have an Al content of 10% to 30%. At least one of the barrier layers disposed between the well layers has a smaller thickness than of the well layers and at least one of the barrier layers placed between the well layers has a thickness and a band gap preventing electrons and holes injected into and confined in a well layer adjacent to the barrier layer from spreading into another adjacent well layer.

Abstract: A pixel structure and manufacturing method thereof are provided. The pixel structure includes: a substrate; an anode electrode layer disposed on the substrate; a plurality of pixel units disposed on the anode electrode layer in rectangular array, where each of the pixel units includes four sub-pixel units arranged in rectangular array, and the emitting colors of the two opposite sub-pixel units at the opposite sides of any two adjacent pixel units are the same; and a cathode electrode layer disposed on the pixel units.

Abstract: A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.

Abstract: A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor.

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

Abstract: A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.

Abstract: Disclosed is a near UV light emitting device. The light emitting device includes an n-type contact layer, a p-type contact layer, an active area of a multi-quantum well structure disposed between the n-type contact layer and the p-type contact layer, and at least one electron control layer disposed between the n-type contact layer and the active area. Each of the n-type contact layer and the p-type contact layer includes an AlInGaN or AlGaN layer, and the electron control layer is formed of AlInGaN or AlGaN. In addition, the electron control layer contains a larger amount of Al than adjacent layers to obstruct flow of electrons moving into the active area. Accordingly, electron mobility is deteriorated, thereby improving recombination rate of electrons and holes in the active area.

Abstract: An exemplary embodiment of the present invention provides a method for preparing an organic light-emitting device, comprising the steps of: 1) forming a spacer pattern on a first electrode formed on a substrate; 2) forming an organic material layer and a second electrode; 3) exposing the first electrode by forming an encapsulation thin film and then etching at least one portion of the encapsulation thin film; and 4) forming an auxiliary electrode which is electrically connected to the first electrode exposed in the step 3). The organic light-emitting device according to the exemplary embodiment of the present invention may solve problems of a voltage drop due to resistance of a transparent electrode in a longitudinal direction and of resultant brightness non-uniformity of the diode.

Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

Abstract: A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal.