Patents Examined by Joseph J Lauture
  • Patent number: 12047086
    Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: July 23, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Paul M. Astrachan, Lingli Zhang, John L. Melanson, James Kelton
  • Patent number: 12047087
    Abstract: An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: July 23, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tadashi Minotani, Kenichi Matsunaga
  • Patent number: 12047088
    Abstract: A data processing system can include a first IC including one or more A/D converters that receive analog inputs from one or more sensors and generate corresponding digital data, a second IC including one or more processing elements that operate on the digital data, and communication circuitry, coupled between the one or more A/D converters and processing elements, that includes a packetizer on the first IC that receives samples and sample data from the one or more A/D converters and assembles each sample and corresponding sample data into a packet, a primary physical interface on the first IC that communicates the packet to a secondary physical interface on the second IC, and a de-packetizer that on the second IC that receives the packet, de-packetizes it, and delivers the sample and sample data to the one or more processing elements.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: July 23, 2024
    Assignee: Apple Inc.
    Inventors: Jose V Santos Martinez, Yongxuan Hu, Nileshbhai J Shah
  • Patent number: 12039421
    Abstract: An apparatus to facilitate deep learning numeric data and sparse matrix compression is disclosed. The apparatus includes a processor comprising a compression engine to: receive a data packet comprising a plurality of cycles of data samples, and for each cycle of the data samples: pass the data samples of the cycle to a compressor dictionary; identify, from the compressor dictionary, tags for each of the data samples, wherein the compressor dictionary comprises at least a first tag for data having a value of zero and a second tag for data having a value of one; and compress the data samples into compressed cycle data by storing the tags as compressed data, wherein the data samples identified with the first tag are compressed using the first tag and the data samples identified with the second tag are compressed using the second tag at the same time as values of the data samples identified with the first tag or the second tag are excluded from the compressed cycle data.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: July 16, 2024
    Assignee: INTEL CORPORATION
    Inventors: Yingyu Miao, Ning Xue
  • Patent number: 12040816
    Abstract: A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: July 16, 2024
    Assignee: Apple Inc.
    Inventor: Antonio Passamani
  • Patent number: 12034412
    Abstract: An amplifier includes a first stage and a second stage. The first stage includes a first output and a second output. The second stage includes an output, a first transistor and a second transistor. The first transistor includes a drain coupled to the first output of the first stage, and a source coupled to the output of the second stage. The second transistor includes a drain coupled to the second output of the first stage, and a gate coupled to the output of the second stage.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: July 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Sankman
  • Patent number: 12034462
    Abstract: This disclosure provides methods, devices, and systems for data compression. The present implementations more specifically relate to encoding techniques for compressing probability tables used for entropy coding. In some aspects, an entropy encoder may encode a probability table so that one or more contexts are represented by fewer bits than would otherwise be needed to represent the frequency of each symbol as a proportion of the total frequency of all symbols associated with such contexts. For example, if a given row of the probability table (prior to encoding) includes a number (M) of entries each having a binary value represented by a number (K) of bits, the same row of entries may be represented by fewer than M*K bits in the encoded probability table.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 9, 2024
    Assignee: Synaptics Incorporated
    Inventor: Scott Liam Ransom
  • Patent number: 12028092
    Abstract: A frequency delta-sigma modulation signal output circuit includes: a phase modulation circuit configured to generate n delay signals obtained by delaying a measurement target signal, n being an integer of 2 or more, and generate a phase modulation signal by randomly selecting one of the n delay signals in synchronization with the measurement target signal; and a frequency ratio digital conversion circuit configured to generate a frequency delta-sigma modulation signal using a reference signal and the phase modulation signal.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: July 2, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Masayoshi Todorokihara
  • Patent number: 12021549
    Abstract: Provided is a technique for converting an integer value sequence for encoding/decoding which allows an integer value sequence having a distribution including small values other than a zero value and greatly biased to small values to be encoded with a small average bit number. Provided are: a unary coding unit which subjects an input sequence of non-negative integer values to unary coding to obtain a unary code sequence; a bit reversing unit which replaces a bit value ‘0’ with a bit value ‘1’ and a bit value ‘1’ with a bit value ‘0’ in the bits in the unary code sequence to obtain a replaced code sequence; and a unary decoding unit which subjects the replaced code sequence to unary decoding to obtain a sequence of non-negative integer values.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 25, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Ryosuke Sugiura, Takehiro Moriya, Yutaka Kamamoto
  • Patent number: 12015411
    Abstract: A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: June 18, 2024
    Assignee: Synopsys, Inc.
    Inventors: Emil Gizdarski, Anubhav Sinha
  • Patent number: 12009579
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Disclosed is a cover device configured to protect an antenna device embedded in an electronic device to radiate a beam of an ultra-high frequency band, the cover device including: a cover frame including a window area corresponding to a radiation area of the antenna device; and a functional structure disposed in the window area on the cover frame and having a stacked structure comprising one or more functional layers.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: June 11, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghoon Park, Juneseok Lee, Dohyuk Ha, Jungyub Lee, Jinsu Heo, Youngju Lee
  • Patent number: 12009829
    Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: June 11, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: John L. Melanson, Lingli Zhang, Paul M. Astrachan, James Kelton
  • Patent number: 12003255
    Abstract: A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number Nd of bits, decomposing the sample into a plurality of binary words of parameterizable bit size Np, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 4, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Johannes Christian Thiele, Olivier Bichler, Marc Duranton, Vincent Lorrain
  • Patent number: 12003250
    Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeongjoon Ko, Jaehyun Park, Junhan Bae, Gyeongseok Song, Jongjae Ryu
  • Patent number: 12003019
    Abstract: A portable or wearable electronic device can include a device housing defining an internal volume, and an electronic component disposed in the internal volume. The electronic component can be an input component and can have a component housing. The electronic device can also include an antenna feed assembly disposed in the internal volume. The antenna feed assembly can include a conductive grounding component electrically connected to the component housing and the device housing, and an antenna feed component electrically connected to the grounding component and disposed adjacent to the component housing. The conductive grounding component can surround a first major surface and a second major surface of the component housing.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 4, 2024
    Assignee: APPLE INC.
    Inventors: Erik G. de Jong, Junlin Mu, Sameer Pandya, Patrick J. Crowley, Antonio F. Herrera, James G. Horiuchi, Sherry Tang, Mario Martinis
  • Patent number: 11997570
    Abstract: A method is closed for context-based compression and reconstruction of data transmitted from a wireless node in an IOT system, according to some embodiments. The method includes a server receiving communications from a sender node. The communication includes truncated data comprising a sender node address, wherein the truncated data does not include an identifier of a physical premises associated with the sender node. The server accesses a lookup table comprising plurality of entries mapping sender node addresses to identifiers of physical premises. The server retrieves an identifier of a physical premises corresponding to node, according to the lookup table and appends the identifier of the physical premises to the sender address to reconstruct the full sender address.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: May 28, 2024
    Inventors: Hendrik J Volkerink, Ajay Khoche
  • Patent number: 11996858
    Abstract: A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more transistors may control a swing of a clock signal to provide a swing controlled clock signal to an amplification portion of the comparator circuit. The swing controlled clock therefor may be used to control the speed of the comparator circuit (e.g., an amplification phase) based on a level of noise in the circuit. The swing controlled clock may further be used to align an output common voltage of the comparator circuit with switching voltages of downstream logic cells (e.g., inverters) connected to the comparator circuit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: May 28, 2024
    Assignee: Retym, Inc.
    Inventors: Roee Eitan, Yaakov Dayan, Yosi Sanhedrai, Aviv Berg, Esther T. Fridman, Kirill Blum
  • Patent number: 11990669
    Abstract: Base station antennas include first through fourth radio frequency (“RF”) ports, a plurality of first combiners that are coupled to the first and second RF ports, a plurality of second combiners that are coupled to the third and fourth RF ports, and an array that includes a plurality of radiating elements that have first through fourth radiators, where first and second radiators of each radiating element are coupled to a respective one of the first combiners, and third and fourth radiators of each radiating element are coupled to respective ones of the second combiners.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: May 21, 2024
    Assignee: CommScope Technologies LLC
    Inventors: Peter J. Bisiules, Mohammad Vatankhah Varnoosfaderani, Sammit Patel
  • Patent number: 11984423
    Abstract: This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: May 14, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Sandra Louise Petty-Weeks, Guohao Zhang, Hardik Bhupendra Modi
  • Patent number: 11979168
    Abstract: A method for improving performance of a superconducting, flux-quantizing analog to digital converter (SFADC), comprising the following steps. The first step involves providing a known digitally-modulated signal as an input to the SFADC. Another step provides for generating an output with the SFADC based on the known digitally-modulated signal. Another step provides for comparing the characteristics of the output with ideal characteristics to identify an individual rapid single flux quantum (RSFQ) element of the SFADC that is contributing one or more of noise and error to the output. Another step provides for altering one or more of a bias, a delay, and a temperature of the individual RSFQ element to reduce one or more of the noise and the error.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: May 7, 2024
    Assignee: United States of America represented by the Secretary of the Navy
    Inventor: Brian A. Higa