Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Abstract: A method, a system, and a computer program product for decompressing data. One or more compressed blocks in a set of stored compressed blocks responsive to a request to access data in the set of stored compressed blocks are identified. String prefixes inside the identified compressed blocks are decompressed using front coding. String suffixes inside the identified compressed blocks are decompressed using a re-pair decompression. Uncompressed data is generated.

Abstract: An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.

Abstract: Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Abstract: A cross-dipole radiating element includes first and second polymer-based coplanar waveguide feed stalks, and first and second pairs of polymer-based radiating arms, which are supported by and electrically coupled to the first and second coplanar waveguide feed stalks. These polymer-based feed stalks and radiating arms are configured as a unitary polymer substrate, which is selectively metallized to define a cross-dipole radiating element. The first and second feed stalks may be configured as finite grounded coplanar waveguide (GCPW) feed stalks, which are spaced-apart from each other on an underlying polymer base. The unitary polymer substrate may include the polymer base.

Abstract: Beam forming antennas for base station applications are configured as dielectric resonator antennas (DRAs) having arrays of dielectric resonator radiating elements (DRRE) therein with dual-polarized radiating properties. Each DRRE includes a dielectric radiating element (DRE) electromagnetically coupled by a resonant cavity to a respective cross-polarized feed network, which is responsive to first and second radio frequency (RF) input feed signals. Each resonant cavity may be configured as a polymer-filled resonant cavity, and each DRE may be configured as a cylindrically-shaped or dome-shaped dielectric radiating element.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.

Abstract: A method for pre-processing files that can improve file compression rates of existing general-purpose lossless file compression algorithms, particularly for files on which traditional algorithms perform poorly. The elementary cellular automata (CA) pre-processing technique involves finding an optimal CA state that can be used to transform an original file into a format (i.e., an intermediary file) that is more amenable to compression than the original file format. This technique is applicable to multiple file types and may be used to enhance multiple compression algorithms. Evaluation on generated files, as well as samples selected from online text repositories, finds that the CA pre-processing technique improves compression rates by up to 4% and shows promising results for assisting in compressing data that typically induce worst-case behavior in standard compression algorithms.

Abstract: Embodiments of the present invention provides an antenna and an antenna system. The antenna includes a body member, a head member integrally connected to a first edge of the body member, wherein the head member forms a fold having a first angle towards the front face of the body member, and a first arm member and a second arm member, wherein the first arm member and the second arm member are integrally connected to the body member corresponding to the second edge and the third edge of the body member, and wherein the set of arm members each form a fold having a second angle towards the front face of the body member.

Abstract: A method of compressing digital signal data obtained from a signal is described. The method includes: receiving digital signal data associated with a signal and/or generating digital signal data based on a signal; transforming the digital signal data into a transform domain, thereby generating transformed digital signal data; determining at least one characteristic parameter based on the transformed digital signal data by an artificial intelligence circuit; detecting and/or classifying at least one wanted signal portion based on the at least one characteristic parameter by the artificial intelligence circuit; and storing only a subset of the digital signal data that is associated with the at least one wanted signal portion. Further, a signal compressor circuit for compressing digital signal data obtained from a signal and a computer program are described.

Abstract: The described technology is generally directed towards a sensor output digitizer. The sensor output digitizer can comprise a multiplexer stage, a multi-stage analog to digital converter, and a digital output combiner. The multiplexer stage can be configured to sequentially select sensor outputs from one or more sensors, resulting in a stream of selected sensor outputs. The multi-stage analog to digital converter can be coupled with the multiplexer stage, and can be configured to convert the stream of selected sensor outputs into a stream of digitized outputs. The digital output combiner can be configured to re-scale and sum intermediate outputs of the multi-stage analog to digital converter to produce a stream of digitized sensor outputs.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: This description relates generally to piecewise temperature compensation. In an example, a circuit includes a knee code selector that can be configured to set a knee point temperature for a correction current responsive to a respective knee point temperature code of knee point temperature codes and a respective temperature sense signal of temperature sense signals. The circuit includes an output circuit that can be configured to provide the correction current responsive to the respective temperature sense signal and temperature voltages, and a trim digital to analog converter (DAC) that can be configured to provide a piecewise compensation current responsive to the correction current and a respective trim code of trim codes.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.

Abstract: A multi-band antenna has a feed point, a grounding location, a first portion for low band operation, a second portion for low band operation, and one or more portions for high band operation. The ground reference of the feed point for the multi-band antenna is connected to a separate object that may provide a base for the multi-band antenna. The feed point of the multi-band antenna may be spaced above the base and have a space between the feed point and a location for the ground point. The low band portion has multiple resonances that are often odd multiples of the lowest resonant response. The portions that resonant most dominantly in the high band often have multiple resonances that are even multiples of the lowest high band resonance. The multi-band antenna has resonances spaced closely enough to appear to be a wide band antenna above the fundamental high band resonance.

Abstract: A combined cellular/GNSS (global navigation satellite systems) antenna is provided. The combined cellular/GNSS antenna comprises an external area and an internal area delineated by a circumference of a circle. The combined cellular GNSS antenna further comprises a cellular antenna and a GNSS antenna. The cellular antenna comprises a set of cellular radiators disposed in the external area and connected to a cellular feeding network for excitation of the set of cellular radiators. The GNSS antenna comprises radiation elements disposed in the internal area and has a center located substantially at a center of the circle.

Abstract: There are provided a signal generation unit that generates a predetermined digital signal, a level conversion unit that converts a level of the digital signal generated by the signal generation unit, a DA converter that converts the digital signal of which the level is converted by the level conversion unit into an analog signal in a predetermined intermediate frequency bandwidth, and a control unit that creates correction data for correcting a linearity of a level of an output signal of the DA converter for all frequencies to be used, based on actual data which is data of a level of an actual output signal when a setting of the level of the output signal of the DA converter is changed at a predetermined level interval, at a predetermined frequency, and converts a level of an input signal of the DA converter with the correction data.