Abstract: A multiband antenna, having a reflector, and a first array of first radiating elements having a first operational frequency band, the first radiating elements being a plurality of dipole arms, each dipole arm including a plurality of conductive segments coupled in series by a plurality of inductive elements; and a second array of second radiating elements having a second operational frequency band, wherein the plurality of conductive segments each have a length less than one-half wavelength at the second operational frequency band.

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction (304): an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC comprises a plurality of N-bit comparator latches that are each locally time-interleaved with at least a pair of latches and configured to function in a complementary manner and provide a combined complementary output.

Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.

Abstract: Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period.

Abstract: Systems and methods which provide an antenna in a chip-and-package distributed configuration as disclosed. Chip-and-package distributed antenna configurations of embodiments comprise an on-chip integrated circuit component and an in-package component. For example, embodiments of a chip-and-package distributed antenna comprise an exciting element on chip (i.e., formed as an integrated component in an integrated circuit die) and a primary radiator in package (i.e., disposed within an package while being external to the integrated circuit die). The on-chip exciting element may be configured to excite electromagnetic waves and to provide relatively wide bandwidth operation while occupying a relatively small area of the die. The in-package primary radiator may be configured to leverage the relatively large space in the integrated circuit product package to enhance the gain and/or configure the radiation pattern of RF signals with respect to the exciting element.

Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Abstract: A gamma correction digital-to-analog converter (DAC) includes a first DAC circuit, a second DAC circuit and a voltage generator. The first DAC circuit includes a plurality of first transistors and is configured to receive a plurality of first reference gamma voltages and 1 upper bits of k-bit digital data and generate a first gamma voltage based on the 1 upper bits of the k-bit digital data and the first reference gamma voltages. The second DAC circuit includes a plurality of second transistors and is configured to receive a plurality of second reference gamma voltages and m lower bits of the k-bit digital data and generate a second gamma voltage based on the m lower bits of the k-bit digital data and the second reference gamma voltages.

Abstract: The present disclosure provides a polarized antenna including a waveguide power divider, a waveguide phase shifter and a radiating unit. The waveguide power divider is configured to have an input waveguide for receiving a transmission signal, and first and second output waveguides for distributing and outputting the transmission signal. The waveguide phase shifter is configured to receive two output signals outputted respectively from the first and second output waveguides of the waveguide power divider, to variably change a phase difference between the two input signals, and to output respective changed signals. The radiating unit is configured to receive the respective changed signals from the waveguide phase shifter, and to combine and radiate the respective changed signals as a radio signal.

Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.

Abstract: An end-fire antenna for wideband low form factor applications includes a first metal layer, a second metal layer, and a dielectric layer disposed between the first and second metal layers. An open cavity formed in the dielectric layer that is filled with air, the cavity defined by a pair of sidewalls that extend from an aperture of the cavity to a rear wall of the cavity, where the depth of the aperture is defined between the aperture and the rear wall. The cavity is formed by selecting the width of the aperture of the cavity and the depth of the cavity such that the antenna achieves the same gain during operation irrespective of a variation in the thickness of the antenna.

Abstract: An apparatus for rectifying a resolver output signal may include: a resolver configured to receive an excitation signal and to output a resolver output signal based on the excitation signal, the excitation signal indicating a position of a rotor of a motor; a microprocessor configured to receive a reference rectification signal generated by rectification of the excitation signal and to output a delay signal by delaying the reference rectification signal according to a preset value; and a delay amount detection circuit configured to receive a reference excitation signal generated by rectification of the resolver output signal, to receive the delay signal from the microprocessor, to compare the reference excitation signal with the delay signal, and to output a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor.

Abstract: A processing device is provided which includes a plurality of encoders each configured to compress a portion of data using a different compression algorithm. The processing device also includes one or more processors configured to cause an encoder, of the plurality of encoders, to compress the portion of data when it is determined that the portion of data, which is compressed by another encoder configured to compress the portion of data prior to the encoder in an encoder hierarchy, is not successfully compressed according to a compression metric by the other encoder in the encoder hierarchy. The one or more processors are also configured to prevent the encoder from compressing the portion of data when it is determined that the portion of data is successfully compressed according to the compression metric by the other encoder in the encoder hierarchy.

Abstract: Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a gradient-based optimization approach or other such optimization approach to determine optimized gain error calibration data to compensate for gain mismatch in and between individual parallel time-interleaved ADCs and to determine time-offset calibration data to compensate for timing errors in and between individual parallel time-interleaved ADCs. For example, once a calibration signal is applied to an ADC, the output of the ADC can be analyzed to determine a spectrum of the calibration signal. One or more images (e.g., phasors) of the spectrum can be determined and used to determine initial values of the optimization.

Abstract: A dual-band antenna includes a first conducting path, a filter and a second conducting path. A first end of the first conducting path is connected with an antenna feed port. A first end of the filter is connected with a second end of the first conducting path. A first end of the second conducting path is connected with a second end of the filter.

Abstract: A method and apparatus of video coding using block partitioning process including a binary tree partitioning process are disclosed. The block partitioning structure corresponding to the block partitioning process for a block of video data is derived by parsing a first indicator associated with a current block and determining whether the binary tree partitioning process applies a binary tree partition to the current block based on a value of the first indicator. When it is determined that the binary tree partition is applied to the current block, the current block is always split into two primary sub-blocks with same size or two primary sub-blocks with different sizes. The block partitioning structure represents partitioning the block of video data into final sub-blocks. The block of video data is decoded based on the final sub-blocks decoded according to the block partitioning structure derived.

Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Abstract: A method of video coding using block partitioning process including a binary tree partitioning process is disclosed. The block partitioning process is applied to a block of video data to partition the block into final sub-blocks. Coding process comprising prediction process, transform process or both for the block will be applied at the final sub-blocks level. The binary tree partitioning process can be applied to a given block when an associated indicator has a first value. In another embodiment, the quadtree partitioning process is applied to a block first. The quadtree leaf nodes are further partitioned using one or more stages of binary tree partitioning process. The quadtree partitioning process can be applied to a given block recursively to generate quadtree leaf nodes until a termination condition is met.

Abstract: An antenna having radio-frequency (RF) resonators and methods for fabricating the same are described. In one embodiment, the antenna comprises a physical antenna aperture having an array of antenna elements, where the array of antenna elements includes a plurality of radio-frequency (RF) resonators, with each RF resonator of the plurality of RF resonators having an RF radiating element with a microelectromchanical systems (MEMS) device.

Abstract: The application discloses a combined phase shifter and a multi-band antenna network system. The combined phase shifter includes at least two phase shifters. The phase shifters have different frequency bands. Each phase shifter includes a signal line layer and components that are configured to change a phase of an output port of the signal line layer. The components are slidable relative to the signal layer. A filter circuit is provided at an output port of the signal layer. Output ports of filter circuits corresponding to the at least two phase shifters are connected by a conductor, and perform output using a common output port.