Patents Examined by Joseph J Lauture
  • Patent number: 11025271
    Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 1, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Clara Ka Wah Sung, Meghal Varia, Serag Gadelrab, Cheng-Teh Hsieh, Jason Edward Podaima, Victor Szeto, Richard Boisjoly, Milivoje Aleksic, Tom Longo, In-Suk Chong
  • Patent number: 11025268
    Abstract: An encoding and decoding method for an optical isolation amplifier including an encoder, an optical driver, a light source, an optical detector, and a decoder, and employing sigma-delta modulation technology is provided. The method includes: generating a plurality of first pulses, each having a predetermined pulse width, through the encoder when an input digital signal experiences an input pulse rising or falling edge; outputting an encoded signal having the plurality of first pulses to the optical driver; driving the light source through the optical driver, according to the plurality of first pulses, so as to output an encoded optical signal; generating a detected signal through the optical detector detecting the encoded optical signal, and the detected signal has a plurality of second pulses; and duplicating the input digital signal of the encoder through the decoder, according to the detected signal having the plurality of second pulses.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: June 1, 2021
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Yu-wei Wang, Meng-Tong Tan
  • Patent number: 11018681
    Abstract: Techniques for testing circuits, such as converter circuits, such as digital-to-analog converter circuits (DACs), are described. A digital signal processor (DSP) can generate a waveform, such as sine wave, and apply the sine wave to the circuit under test, e.g., a DAC. The DAC can generate an output and the DSP can regenerate the waveform and determine an accuracy of the DAC such as to determine whether the DAC meets one or more specified criteria. In some example implementations, the tests can be performed using variable voltage amplitude segments.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: May 25, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: David James Hamilton
  • Patent number: 11018438
    Abstract: Disclosed is a telecommunications antenna having a plurality of cloaked low band (LB) and high band (HB) dipoles. The LB and HB dipoles provide cloaking by breaking the dipoles into dipole segments, and providing conductive cloaking elements over the gaps between dipole segments to form a plurality of capacitors along the dipole. The capacitors along the LB dipoles provide a low impedance to LB RF signals and a high impedance to HB signals. The capacitors formed on the HB dipoles provide a low impedance to RF signals and high impedance to harmonics of the LB RF signals. This cross-cloaking of dipoles enables more dense arrangements of LB and HB dipoles on an antenna array face, providing opportunities to arrange, for example, the LB dipoles with an array factor that results in an advantageous fast roll off gain pattern.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 25, 2021
    Assignee: JOHN MEZZALINGUA ASSOCIATES, LLC
    Inventors: Alex Waldauer, Charles Buondelmonte, Taehee Jang, Niranjan Sundararajan, Evan Christopher Wayton, Lance Bamford
  • Patent number: 11018685
    Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo Jin Jang, Yong Lim, Seung Hyun Oh, Jae Hoon Lee
  • Patent number: 11011855
    Abstract: An antenna system includes a dielectric substrate, a first dipole antenna element, a second dipole antenna element, a first additional metal element, a second additional metal element, first conductive via elements, and second conductive via elements. The first dipole antenna element and the first additional metal element are disposed on a first surface of the dielectric substrate. The first dipole antenna element includes a first radiation element and a second radiation element. The second dipole antenna element and the second additional metal element are disposed on a second surface of the dielectric substrate. The second dipole antenna element includes a third radiation element and a fourth radiation element. The first additional metal element is coupled through the first conductive via elements to the third radiation element. The second additional metal element is coupled through the second conductive via elements to the first radiation element.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 18, 2021
    Assignee: WISTRON NEWEB CORP.
    Inventor: Chun-Lin Huang
  • Patent number: 11012084
    Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 18, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Obaida Mohammed Khaled Abu Hilal
  • Patent number: 11005494
    Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 11, 2021
    Assignee: Jariet Technologies, Inc.
    Inventors: Ark-Chew Wong, Richard Dennis Alexander
  • Patent number: 11005190
    Abstract: An antenna array includes a dielectric substrate, a ground metal plane, a first antenna unit, a second antenna unit, a third antenna unit, and a fourth antenna unit. The first antenna unit includes a first metal loop and a first feeding metal element. The first feeding metal element is adjacent to the first metal loop. The second antenna unit includes a second metal loop and a second feeding metal element. The second feeding metal element is adjacent to the second metal loop. The third antenna unit includes a third metal loop and a third feeding metal element. The third feeding metal element is adjacent to the third metal loop. The fourth antenna unit includes a fourth metal loop and a fourth feeding metal element. The fourth feeding metal element is adjacent to the fourth metal loop.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 11, 2021
    Assignee: WISTRON CORP.
    Inventors: Po-Tsang Lin, Ying-Sheng Fang
  • Patent number: 10989830
    Abstract: Buried object locators including an omnidirectional antenna array and a gradient antenna array are disclosed. A locator display may include information associated with a buried object determined based on processing of both omnidirectional antenna array signals and gradient antenna array signals.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: April 27, 2021
    Assignee: SEESCAN, INC.
    Inventors: Mark S. Olsson, Ray Merewether, Michael J. Martin, Ryan B. Levin
  • Patent number: 10985768
    Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 20, 2021
    Assignee: JARIET TECHNOLOGIES, INC.
    Inventors: Ark-Chew Wong, Richard Dennis Alexander, Craig A. Hornbuckle
  • Patent number: 10978793
    Abstract: An antenna includes an antenna substrate comprising a first end and a second end, and an antenna element attached to the antenna substrate. The antenna element is configured to receive communication signals within a partial hemispherical-shaped signal reception region oriented about the first end of the antenna substrate. A signal gain reduction portion is at least partially located between the antenna element and the second end of the antenna substrate, and is configured to reduce signal gain in an opposite partial hemispherical-shaped region oriented about the second end of the antenna substrate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 13, 2021
    Inventor: Shawn Hill
  • Patent number: 10972124
    Abstract: A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 6, 2021
    Assignee: 5 BY 5, LLC
    Inventors: Troy Hill, Rishon Kimber, Travis McDougall
  • Patent number: 10972121
    Abstract: An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 6, 2021
    Assignee: Viavi Solutions Inc.
    Inventor: Sean Hamlin
  • Patent number: 10965303
    Abstract: Techniques for improving a power supply accuracy of a precision data converter system, such as analog-to-digital converter circuits (ADCs) and digital-to-analog converter circuits (DACs). Improving the power supply accuracy can enable a reference voltage to be as large as possible, thereby increasing the signal-to-noise-ratio (SNR). The techniques can also simplify power supply sequencing requirements for the data converter system.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 30, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Richard James Reay, Richard T Owen, Eric C. Welde
  • Patent number: 10965309
    Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 30, 2021
    Assignee: Raytheon Company
    Inventor: Brian A. Gunn
  • Patent number: 10965005
    Abstract: A communication device includes a nonconductive housing, a cable, an antenna structure, and a signal source. The nonconductive housing has a hollow structure. The cable is coupled to the signal source. The cable includes a signaling conductor and a grounding conductor. The antenna structure includes an antenna body and an enclosed radiation element. The antenna body is coupled to the signaling conductor. The antenna body is disposed outside the nonconductive housing. The enclosed radiation element is coupled to the grounding conductor. The enclosed radiation element is disposed inside the nonconductive housing.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 30, 2021
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chun-Lin Huang, Chien-Ting Huang
  • Patent number: 10965307
    Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a program that allow an improvement in the rate of modulation of PWM signals. Pulse width modulation (PWM) is performed to convert one of a 0 or 1 represented by a bit of a pulse density modulation (PDM) signal into which an audio signal has been PDM-modulated, into a maximum-length pulse of a maximum pulse width of a PWM signal having a period equal to the period of the PDM signal, and convert the other of the 0 or 1 of the PDM signal into a minimum-length pulse of a minimum pulse width of the PWM signal at a position adjacent to the center of the period of the PWM signal. The present technology is applicable, for example, to audio reproduction systems that reproduce audio signals.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 30, 2021
    Assignee: SONY CORPORATION
    Inventor: Yoshinori Tamori
  • Patent number: 10965311
    Abstract: Described herein is an improved apparatus for increasing the performance of a ?? modulator, which may function as an ADC. In one embodiment, the ?? modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the ?? modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: March 30, 2021
    Assignee: SiliconIntervention Inc.
    Inventor: A. Martin Mallinson
  • Patent number: 10965310
    Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Meghna Agrawal