Abstract: Disclosed is a low band dipole that has four dipole arms in a cross configuration, and a simplified cloaking structure to substantially prevent interference with radiated RF energy from nearby high band dipoles. Further disclosed is a feed network and dipole stem balun configuration that power divides and combines two distinct RF signals, without the use of a hybrid coupler, so that the four dipole arms collectively radiate the two RF signals respectively at a +45 degree and ?45 degree polarization orientation relative to the orientation of the dipole arms.

Abstract: An end-fire antenna for wideband low form factor applications includes a first metal layer, a second metal layer, and a dielectric layer disposed between the first and second metal layers. An open cavity formed in the dielectric layer that is filled with air, the cavity defined by a pair of sidewalls that extend from an aperture of the cavity to a rear wall of the cavity, where the depth of the aperture is defined between the aperture and the rear wall. The cavity is formed by selecting the width of the aperture of the cavity and the depth of the cavity such that the antenna achieves the same gain during operation irrespective of a variation in the thickness of the antenna.

Abstract: Embodiments of the present invention provides an antenna and an antenna system. The antenna includes a body member, a head member integrally connected to a first edge of the body member, wherein the head member forms a fold having a first angle towards the front face of the body member, and a first arm member and a second arm member, wherein the first arm member and the second arm member are integrally connected to the body member corresponding to the second edge and the third edge of the body member, and wherein the set of arm members each form a fold having a second angle towards the front face of the body member.

Abstract: An information handling system to wirelessly transmit and receive data may include a base chassis including a processor, a memory, and a wireless adapter; a metal C-cover of the base chassis to house a speaker grill, the speaker grill covering a speaker to emit audio waves; the speaker grill formed within the C-cover, the speaker grill including a slot formed around a portion of a perimeter of the speaker grill that physically separates the portion of the speaker grill as a peninsula in the C-cover; a millimeter wave antenna element coupled to a back side of the speaker grill; and a sub-6 GHz antenna element to transmit via the slot formed around the perimeter of the speaker grill; wherein the speaker grill has a mesh pattern of grill openings sized to be transparent to millimeter wave frequencies emitted by the millimeter wave antenna element.

Abstract: A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

Abstract: This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.

Abstract: A system for processing a signal in a signal chain having decentralized embedded power management of components of the signal chain includes an input circuit to generate a measurement signal responsive to a stimulus, where the measurement signal is indicative of a characteristic of the stimulus. The system additionally includes a signal converter circuit coupled to the input circuit to convert the measurement signal to a digital signal according to a timing condition for capturing a sample of the measurement signal. The signal converter includes a control circuit to provide electrical power to the input circuit based on the timing condition and a sampling circuit to capture the sample of the measurement signal responsive to an indicator signal generated by the sensor circuit.

Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.

Abstract: A reference voltage generator comprises a comparator, a digital-to-analog converter (DAC) and a switched capacitor accumulator. The comparator receives a reference voltage input, a feedback input, and a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator can be coupled to a buffer that outputs the feedback input and a reference voltage for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N one-bit DACs coupled to the output of the comparator and N switched capacitor accumulators, each of which is coupled to a unique one-bit DAC.

Abstract: One example method includes file specific compression selection. Compression metrics are generated for a chunk of a file. Using a set of training data, the compression metrics are corrected using a correction factor to determine estimated file compression metrics. A compressor is then selected to compress the file based on at least the estimated file compression metrics.

Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.

Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Abstract: Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.

Abstract: A method of compressing weights of a neural network includes compressing a weight set including the weights of a the neural network, determining modified weight sets by changing at least one of the weights, calculating compression efficiency values for the determined modified weight sets based on a result of compressing the weight set and results of compressing the determined modified weight sets, determining a target weight of the weights satisfying a compression efficiency condition among the weights based on the calculated compression efficiency values, and determining a final compression result by compressing the weights based on a result of replacing the determined target weight.

Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.

Abstract: An excess loop delay compensation (ELDC) technique for use with a successive approximation register (SAR) based quantizer in a continuous time delta-sigma ADC is described. The techniques can efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers. An ELDC circuit can include a charge pump having a digitally programmable capacitance to adjust a gain, such as the gain of the ELDC digital-to-analog converter (DAC) or the gain of the SAR DAC.

Abstract: A ramp generator includes a plurality of switched current sources coupled in parallel between a resistor and ground. A digital ramp control signal generator includes a counter to generate a ramp control signal in response to a clock signal. Each bit of the ramp control signal is coupled to control switching of a respective one of the plurality of switched current sources to generate a ramp signal at an output of the ramp generator. The digital ramp control signal generator is coupled to receive a reset signal to zero the ramp control signal. The digital ramp control signal generator is further coupled to receive a set bits signal to initialize the ramp signal to a preset value after every reset of the ramp control signal to add a DC offset compensation current determined by the preset value to the ramp signal.

Abstract: The present invention relates to an antenna assembly for a beamforming antenna, comprising a reflector and an antenna array that includes a plurality of first radiating elements that are arranged as a first vertically extending array, the first radiating elements extending forwardly from the reflector; and a plurality of second radiating elements that are arranged as a second vertically extending array, the second radiating elements extending forwardly from the reflector. Two adjacent first radiating elements are spaced apart from one another by a first distance, and a first radiating element and an adjacent second radiating element are spaced apart from one another by a second distance. The first distance is substantially equal to the second distance. The antenna assembly further comprises a plurality of parasitic elements that are placed along sides of the first and second of the vertically extending arrays.

Abstract: An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.

Abstract: A broadband dual-polarized antenna integrated high-performance balun. The antenna structure consists of three main parts: radiator, feeding structure and reflector. The radiation element consists of four radiation parts with petal shape, forming two pairs of orthogonal dipole antennas. The feeding structure consists of four circuit boards with separated lines, forming resonant structures corresponding to a balance transformer. The reflector enables to direct the beam, increasing the antenna's orientation.