Patents Examined by Joseph Nguyen
  • Patent number: 7683383
    Abstract: A light emitting device having a circuit protection unit is provided. The circuit protection unit has a low-resistance layer and a potential barrier layer, wherein a barrier potential exists at the interface between the low-resistance layer and the potential barrier layer. The circuit protection unit is electrically connected with the light emitting device. When an electrostatic discharge or excessive forward current is occurred in the light emitting device, the circuit protection unit provides a rectifying function for preventing damages caused by static electricity or excessive forward current to the light emitting device.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: March 23, 2010
    Assignee: Epistar Corporation
    Inventors: Steve Meng-Yuan Hong, Jen-Shui Wang, Tzu-Feng Tseng, Ching-San Tao, Wen-Huang Liu, Min-Hsun Hsieh
  • Patent number: 7683415
    Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 23, 2010
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin-Youn Cho
  • Patent number: 7683420
    Abstract: A nonvolatile memory semiconductor device and a method for manufacturing thereof are provided to avoid deterioration of the tunnel insulating film to increase frequency of writing data on the nonvolatile memory semiconductor device and erasing thereof. Concentration of atomic nitrogen in a tunnel insulating film 151 of a nonvolatile memory semiconductor device 1 is 0.1 to 5 atomic %. In addition, larger amount of atomic nitrogen in the tunnel insulating film 151 is distributed primarily in the interface layer of the tunnel insulating film 151, and concentration of atomic nitrogen in the interface layer is 10 times or more higher than concentration of atomic nitrogen in other portion of the tunnel insulating film 151. Further, density per unit area of atomic nitrogen in the surface of the tunnel insulating film 151 contacting with the floating gate is equal to or lower than 4×1014 atoms/cm2.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: March 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shien Cho
  • Patent number: 7683423
    Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: March 23, 2010
    Inventor: Katsuki Hazama
  • Patent number: 7679085
    Abstract: A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 16, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Woong Gi Jun, Gee Sung Chae, Jae Seok Heo
  • Patent number: 7679098
    Abstract: Edge-emitting light source and method for fabricating an edge-emitting light source. The edge-emitting light source includes a photonic crystal having at least one waveguide region. An edge-emitting semiconductor structure having a light emitting active layer is incorporated within the at least one waveguide region. Light emitted by the edge-emitting semiconductor structure and within the bandgap of the photonic crystal is confined within the waveguide region and guided out of the photonic crystal through the waveguide region.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventor: Scott W. Corzine
  • Patent number: 7679079
    Abstract: Organic thin film transistor and related composite and device structures comprising an organic dielectric medium comprising, for instance, a non-linear optical chromophoric moiety.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: March 16, 2010
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Myung-Han Yoon
  • Patent number: 7675114
    Abstract: In order to obtain an increased avalanche strength, a trench transistor is proposed in which the breakdown location is defined in a trench bottom region below body contact zones. This is done by means of a modulation of the dopant concentration in a drift zone and an insulation layer thickness modulation in the bottom region of the trenches.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 9, 2010
    Assignee: Infineon Technologies AG
    Inventor: Markus Zundel
  • Patent number: 7671457
    Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: March 2, 2010
    Assignee: Amkor Technology, Inc.
    Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Sukianto Rusli
  • Patent number: 7663167
    Abstract: A pixel with a photosensor and a transfer transistor having a split transfer gate. A first section of the transfer gate is connectable to a first voltage source while a second section of the transfer gate is connectable to a second voltage source. Thus, during a charge integration period of a photosensor, the two sections of the transfer gate may be oppositely biased to decrease dark current while controlling blooming of electrons within and out of the pixel cell. During charge transfer the two gate sections may be commonly connected to a positive voltage sufficient to transfer charge from the photosensor to a floating diffusion region.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: February 16, 2010
    Assignee: Aptina Imaging Corp.
    Inventor: John Ladd
  • Patent number: 7663142
    Abstract: To provide a light emitting device capable of promoting an efficiency of taking out light to outside and achieving highly reliable bright image display by lower power consumption, in a light emitting device including a plurality of pixels and including a transistor and a pixel electrode electrically connected to the transistor at each of the plurality of pixels, an insulating film provided below the pixel electrode includes an opening portion an side surface of which is a curved face at a light emitting region. Light emitted from a light emitting element is focused by the curved face provided at the insulating film to reduce propagation thereof in a lateral direction, the efficiency of taking out the light is promoted and therefore, bright image display can be achieved without particularly increasing a current amount to be injected.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoshi Murakami
  • Patent number: 7659580
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: February 9, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Patent number: 7659546
    Abstract: A light emitting device firstly includes a light emitting diode (LED) structure, having a top surface with a light emitting region. The device also has a heterojunction within the device structure, the heterojunction having a p-type and an n-type semiconductor layer, and a plurality of electrodes positioned on the top surface, each being electrically connected to one of the p-type and n-type semiconductor layers. At least a first and a second electrodes are connected to a same type semiconductor layer and are physically separated from each other. The device further includes a first and a second heterojunction regions within the heterojunction, each being respectively defined between one of the first and second electrodes and one of the other electrodes connected to the other type semiconductor layer. The first and second heterojunction regions are alternatively driven for emitting lights in the time domain.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: February 9, 2010
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Ming Lu, Geoffrey Wen Tai Shuy
  • Patent number: 7655957
    Abstract: A submount for a solid state lighting package includes a support member having upper and lower surfaces, a first side surface, and a second side surface opposite the first side surface, a first electrical bondpad on the upper surface of the support member and having a first bonding region proximate the first side surface of the support member and a second bonding region extending toward the second side surface of the support member, and a second electrical bondpad on the upper surface of the support member having a die mounting region proximate the first side surface of the support member and an extension region extending toward the second side surface of the support member. The die mounting region of the second electrical bondpad may be configured to receive an electronic device. The submount further includes a third electrical bondpad on the upper surface of the support member and positioned between the second side surface of the support member and the die mounting region of the second electrical bondpad.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: February 2, 2010
    Assignee: Cree, Inc.
    Inventors: Ban P. Loh, Nicholas Medendorp, Jr., Bernd Keller
  • Patent number: 7652292
    Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: January 26, 2010
    Assignee: NEC Corporation
    Inventor: Kazushige Takechi
  • Patent number: 7649249
    Abstract: An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to the other major surface. The semiconductor device can be manufactured from a semiconductor wafer by creating holes that penetrate partway through the wafer, filling the holes with metal to form the electrically conductive members and thermally conductive members, and then grinding the lower surface of the wafer to expose the ends of the electrically conductive members and thermally conductive members before dicing the wafer into chips. The thermally conductive members improve heat dissipation performance when semiconductor chips of this type are combined into a stacked multichip package.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: January 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Noguchi
  • Patent number: 7642632
    Abstract: A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (?) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (?) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to t
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: January 5, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Min Kang
  • Patent number: 7642583
    Abstract: A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventor: Hiroshige Hirano
  • Patent number: 7638859
    Abstract: Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: December 29, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Cheng Lu, Ming-Hsing Tsai
  • Patent number: 7635874
    Abstract: A light-emitting diode (LED) in accordance with the invention includes an edge-emitting LED stack having an external emitting surface from which light is emitted, and a reflective element that is located adjacent to at least one external surface of the LED stack other than the external emitting surface. The reflective element receives light that is generated inside the LED stack and reflects the received light back into the LED stack. At least a portion of the reflected light is then emitted from the external emitting surface.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: December 22, 2009
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Jeffrey N. Miller, Steven D. Lester, Virginia M. Robbins