Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

Abstract: A semiconductor memory device includes a plurality of memory cells for storing data and a selector for selecting at least one memory cell from the plurality of memory cells based on an address signal. The semiconductor memory device includes a transient detecting unit for outputting a first signal in accordance with a transient of the address signal; and a generator for generating a second signal indicating a wait for accessing a memory cell based on the first signal and a clock signal.

Abstract: A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in V.sub.CC. Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure V.sub.CC remains within strict tolerances.

Abstract: A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings.

Abstract: The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line.

Abstract: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off.

Abstract: An FPGA including SRAM memory cells, each having a latch configured so that both read and write signals are provided through the data path connection. By providing both read and write through the data path, the FPGA further includes only a single decoder to control pass gates connected to the memory cells during read and write. To prevent voltages during write from damaging pass gates in the data path, the FPGA further includes a modified power supply to provide voltages ranging from V.sub.DD to V.sub.SS to the memory cell transistors during read, while providing a reduced voltage range during write to enable memory cell states to more easily be altered.

Abstract: A semiconductor memory, such as Dynamic Random Access Memory (DRAM), is provided for replacing a defective memory cell with a spare memory cell. The DRAM includes a main section which has a memory cell array with a plurality of memory cells arranged in an array. A spare section having a spare memory cell array also includes a plurality of memory cells arranged in an array. An address decoder specifies addresses, respectively, of the main section array and the spare section array. A defective bit replacement control circuit is connected to the address decoder and includes a plurality of electrically rewritable nonvolatile memory cells. The address decoder conducts a change-over operation for specifying an address of the first or second arrays according to a storage state, i.e., contents, of electrically rewritable nonvolatile memory cells.

Abstract: A circuit and method for determining the exact time at which data begins to be written to a memory cell. A write sensing circuit is connected to a data input line. When data is presented on the data input line for writing to the memory cell, the write sensing circuit outputs a write start signal indicating that data is being presented to memory cells for writing. The actual start time of a write to a memory cell is therefore accurately timed based on the start of the write to the memory cell itself. This provides the advantage that the change in state of the data is directly sensed as the factor for measuring the start time of a write to a memory cell. The data can be sensed either directly from the bit lines or, alternatively, from a write data bus.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A non-volatile memory module includes a charging circuit, a battery couple to the charging circuit, a volatile memory and an electronic switch coupled between the volatile memory and the battery.

Abstract: A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Abstract: A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

Abstract: The present invention relates to a flash memory device and more particularly to a flash memory device which can improve the performance of the memory cell due to the decrease in the verification time by performing the verification in parallel by selecting a plurality of addresses and then utilizing an integer multiple number of two or more of conventional verify modes at the time of verify mode.

Abstract: A method for setting the threshold voltage of a reference memory cell of a memory device is described, the reference memory cell being used as a reference current generator for generating a reference current which is compared by a sensing circuit of the memory device with currents sunk by memory cells to be sensed, belonging to a memory matrix of the memory device. The method comprises a first step in which the reference memory cell is submitted to a change in its threshold voltage, and a second step in which the threshold voltage of the reference memory cell is verified. The second step provides for performing a sensing of the reference memory cell using a memory cell with known threshold voltage belonging to the memory matrix as a reference current generator for generating a current which is compared by the sensing circuit with the current sunk by the reference memory cell.

Abstract: A semiconductor memory having a function that set/reset information is directly written into each of the memory cells is disclosed. The semiconductor memory device of the present invention comprises word lines, bit lines, set/reset lines and switch circuits each of which is coupled to one of the set/reset lines for applying either a first potential or a second potential in response to a control signal. The semiconductor memory device further includes memory cells for storing data therein. Each of the memory cells has a first node coupled to one of the word lines, a second node coupled to one of the bit lines, a third node coupled to receive the first potential, and a forth node coupled to one of the set/reset lines.

Abstract: A semiconductor integrated circuit device with a copy-preventive function comprises a memory for storing data to be used by users, an input unit for performing various logical operations on at least one input information fed externally and accessing the memory, an output unit for performing various logical operations on the data at the time of supplying the data from the memory, a judging unit for comparing at least one of the state of the input information, the logical state of the input unit, the logical state of the output unit, and the state of data provided by the output unit with specific judgment information and indicating the result of comparison, and a control unit that when the result indicated by the judging unit reveals that the at least one of the states is consistent with a specific state, acts at least on the output unit so as to prevent data stored in the memory from being supplied normally.

Abstract: A flash memory includes a flash transistor array, a wordline decoder, a bitline decoder, a sourceline decoder and a read/write controller. The read/write controller has a voltage terminal to receive an input voltage and a data terminal to receive a new data signal. A sense amplifier is coupled to the bitline decoder and configured to sense a signal on a selected bitline and to generate an internal old data signal. A data comparator is coupled to the data terminal and the sense amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to read a selected cell in the flash transistor array, a program set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts.

Abstract: The device and process of this invention provide for eliminating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.