Abstract: In an I/O pulse processing apparatus associated with a microcomputer, an I/O processing task is required by the microcomputer in the form of the combination of task microinstructions, each of which includes an instruction code specifying one of basic I/O processing operations and a code for specifying one or two registers necessary for executing the basic I/O processing operation. The apparatus includes an I/O task register part having a task register group consisting of plural task registers, which store the task microinstructions supplied from the microcomputer and necessary for executing the task required thereby, and a task signal generator for producing address signals for the task register group, according to which the task microinstructions are read out successively from the task register group.

Abstract: A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode.The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

Abstract: A modular switching system for connecting a plurality of digital computers to a plurality of computer memories, employing interconnecting digital switching modules. Each module has the capability of recognizing an access request to a computer memory by recognizing a generated address within a range of addresses assigned to that computer memory. The digital switching modules are interconnected with a priority network which permits arbitration between simultaneous requests for access by several digital computers to the same computer memory.

Abstract: A memory control system connects, by a single memory bus, plural memories that are individually operable and plural memory access source units so as to effectively use the single memory bus. The memory control system includes a memory request acceptance unit that permits each memory access source unit access to the memories on the basis of the type of access request from each memory access source unit and the type of access request in the memory that is in operation.

Abstract: A portable electronic device of this invention has a control CPU (Central Processing Unit) and a data memory. The data memory is divided into a plurality of areas, and each area consists of a data area and an attribute area indicating an attribute of the data area. The attribute area consists of a first flag indicating whether or not data is stored in the data area, a second flag indicating whether or not data written in the data area is valid, and a third flag indicating whether or not data written in the data area is stored as a block. When an instruction supplied from a host system is a valid-data rearrangement instruction, the control CPU refers to the second flag, and sets a first flag of a data area whose second flag indicates that data is invalid to indicate that data is unwritten, thus rear-ranging valid data of the data memory so that no invalid data area is present between valid data areas.

Abstract: A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Abstract: A communication control apparatus wherein the version number of a communication control program in a packet accepted by a receive circuit is compared at a comparator with that of the local station. When the version for the local station is determined to be older than the version for the remote station, the apparatus receives the latest communication control program from the remote station and stores it in a rewritable memory, thereby allowing communication using the latest version.

Abstract: A multiport memory includes first and second signal lines. Each signal line can simultaneously and independently access a particular address during a read memory portion of a clock pulse whereas both signal lines are used to write data to one address during another portion of the clock pulse.

Abstract: A system and method for implementing virtual memory in a computer system, wherein a table containing entries indicative of the correlation of virtual memory addresses to physical memory addresses is maintained in main memory, and translation descriptors, derived from the translation table entries, for a variable group of virtual addresses, is maintained in a high speed memory. Portions of a virtual address to be translated are compared to the translation descriptors in the high speed memory. If a matching translation descriptor is found, the corresponding physical address is determined by combining a portion of the virtual address with a portion of the matching translation descriptor. If a matching descriptor is not found, a software algorithm is employed to generate a translation descriptor for the virtual address from the table in main memory. The generated translation descriptor is then installed in the high speed memory, the comparison repeated, and the corresponding physical address generated.

Abstract: A multi-node data processing system is described in which each node (10-13) includes a processor (PROC) and an inter-node switch (INS). In operation, only one INS is active. The active INS is configured to act as a star coupler, receiving messages from any of the nodes and broadcasting each message to all the nodes including the node in which that INS is located. Each non-active INS is configured to route messages from the local processor to the active INS, and to route incoming messages broadcast by the active INS to the local processor. The system can be reconfigured to make a different INS active.

Abstract: A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predetermined state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory.

Abstract: Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.The pointer directs memory accessing to prevent conflicts.

Abstract: An asychronous state machine waits a variable length of time after first detecting a change in input state before initiating a machine state change, the new machine state being a function of the previous machine state and the input state at the end of the waiting time, thereby allowing multiple, non-simultaneous input changes to occur during said waiting time without initiating intermediate state changes. The waiting time is a function of the current state of the machine. One state variable of a set characterizing the current state of the machine indicates whether the current state is an interim state in a sequence of states occurring after an input state change. Following a machine state change, this sequencing state variable initiates a subsequent state change, in the absence of any further input state changes, when the sequencing state variable associated with the current machine state indicates that the current machine state is such an interim state of a sequence of states.

Abstract: A data processing system in which a host processor is connected to a plurality of remote processing devices over a common communication channel in which a number of the remote processors are commonly connected to a transceiver for transmitting and receiving data over the communication channel. Switching members on each of the remote processing devices select a pair of communication lines coupled to a priority resolving circuit for transmitting request to send signals and receiving clear to send signals, thereby enabling the remote processing devices to transmit and receive data over the communication channel.

Abstract: A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.