Abstract: A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region.

Abstract: An FFS mode LCD device is disclosed which includes: a substrate; gate and data lines arranged to cross each other on the substrate and define white, red, green and blue sub-pixels with asymmetric areas; first through fourth thin film transistors connected to the white, red, green and blue sub-pixels; common electrodes disposed in the white, red, green and blue sub-pixels; and white, red, green and blue pixel electrodes disposed to overlap with the common electrodes within the white, red, green and blue sub-pixels.

Abstract: The present invention provides a LED light source for increasing a light emitting angle and a manufacturing method thereof, as well as a backlight source and a display device. A LED light source comprises a circuit board, a LED which is directly fixed on and electrically connected to the circuit board, and a packaging piece for packaging a LED light emitting chip. A prism film with a prism micro-structure may be arranged between the packaging piece and the LED.

Abstract: A mount substrate includes: an insulation substrate containing resin and glass; connection conductors formed on a surface of the insulation substrate; a first white resist layer that covers the connection conductors; and a second white resist layer that covers the first white resist. Each of the connection conductors includes a copper foil and a plating layer partly formed on the copper foil. The plating layer is formed of metal having oxidation-resistant and corrosion-resistant characteristics higher than those of copper. The first white resist layer is formed with first openings that respectively expose the plating layers of the connection conductors. The second white resist layer covers a periphery of each plating layer of the connection conductors in planar view.

Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an are enclosed by the oxide material formed in the opening.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure.

Abstract: A stacked semiconductor device includes: a plurality of stacked integrated-circuit chips that are to be mounted onto a substrate and including at least one power-supply target chip; a decoupling through-electrode transmission line including a decoupling power-supply-side through-electrode wiring line coupled to a power-supply terminal of the at least one power-supply target chip and a decoupling ground-side through-electrode wiring line coupled to a ground terminal of the at least one power-supply target chip; a resistor and a capacitor provided one of the a plurality of integrated-circuit chips that is located at a termination of the decoupling through-electrode transmission line, the resistor having an impedance substantially equal to a characteristic impedance of the decoupling through-electrode transmission line, wherein the resistor and the capacitor are coupled in series.

Abstract: The invention provides a flexible transparent solar cell and a production process of the same, and belongs to the technical field of solar cell. The flexible transparent solar cell comprises: a flexible transparent substrate, a transparent front-electrode, a cell unit, a transparent back-electrode and a transparent encapsulating layer, which are disposed in this order; the transparent front-electrode comprising a metallic grid thin film layer and a graphene layer; and the transparent back-electrode comprising a nano metal layer and a graphene layer. The invention can be used in production of flexible transparent solar cell, in order to improve conductivity and transparency of solar cells.

Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.

Abstract: A method of forming a flexible display apparatus includes: forming a flexible substrate on a support substrate; forming a light-emitting diode on the flexible substrate; forming a first encapsulation layer on the light-emitting diode; forming a second encapsulation layer; bonding the first encapsulation layer to the second encapsulation layer using an adhesive layer between the first encapsulation layer and the second encapsulation layer; separating the support substrate from the flexible substrate and cutting the flexible substrate to form the flexible display apparatus; and forming a polarizing plate on the second encapsulation layer.

Abstract: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract: A micro-electro-mechanical system (MEMS) chip package including a circuit substrate, a driving chip and a MEMS sensor is provided. The circuit substrate has a first surface and a second surface opposite thereto. The driving chip is embedded within the circuit substrate and includes a first signal transmission electrode, a second signal transmission electrode and a third signal transmission electrode. The MEMS sensor is disposed on the first surface of the circuit substrate. The circuit substrate includes at least one first conductive wiring electrically connected with the first signal transmission electrode and at least one second conductive wiring electrically connected with the second signal transmission electrode. The first conductive wiring is merely exposed at the first surface and the second conductive wiring is merely exposed at the second surface. The MEMS sensor is electrically connected with the first signal transmission electrode through the first conductive wiring.

Abstract: A light emitting element having a light emitting layer, an electro-conductive reflection film that reflects light emitted from the light emitting layer and a substrate in this order, wherein the electro-conductive reflection film contains metal nanoparticles.

Abstract: A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a thin-film drive transistor. Each display pixel may have thin-film transistors and capacitor structures that form a circuit for compensating the drive transistor for threshold voltage variations. The capacitor structures may be formed from interleaved stacked conductive plates. The conductive plates may be formed from layers of material that are used in forming the drive transistor and other thin-film transistors such as a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and interposed dielectric layers.

Abstract: A touch organic light emitting diode (OLED) display device, including: a thin film transistor formed on one side of a substrate, a touch signal feedback layer formed on the thin film transistor, a luminous substrate provided on the touch signal feedback layer, and a touch signal receiving layer formed on the other side of the substrate. An anode layer of the luminous substrate is connected to a drain electrode of the thin film transistor. As to the touch-sensitive OLED display device, a touch screen and an OLED display portion are prepared integratedly, so that the weight and thickness of the display itself are greatly reduced, and the production cost is saved. A manufacturing method of the touch-sensitive OLED display device is further disclosed.

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

Abstract: A TN-type array substrate and a fabrication method thereof, and a display device, the fabrication method of the TN-type array substrate includes: a step of forming a first metal layer, a gate insulating layer, an active layer, a second metal layer and a transparent conductive layer on a substrate, wherein the first metal layer includes a gate electrode, the second metal layer includes a data line, the transparent conductive layer includes a pixel electrode; and wherein the forming the second metal layer and the transparent conductive layer includes: sequentially forming a transparent conductive thin film and a metal thin film on the substrate; performing one-off patterning process on the transparent conductive thin film and the metal thin film to form a thin film transistor (TFT) channel region, the transparent conductive layer and the second metal layer.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.