Abstract: A display device is provided, and includes a display panel, a multi-layered polarizer layer, and a cover layer. The display panel has a substrate with two opposite first edges. The multi-layered polarizer layer is disposed on the display panel and has a bottom layer with two opposite second edges corresponding to the two opposite first edges respectively. The cover layer is disposed on the multi-layered polarizer layer. A distance between one of the two opposite first edges and one of the two opposite second edges corresponding to the one of the two opposite first edges is greater than 0 and less than or equal to 5 millimeters.

Abstract: A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Abstract: A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

Abstract: Methods for forming light emitting diodes (LEDs) that leverage cavity profiles and induced stresses to alter emitted wavelengths of the LEDs. In some embodiments, the method includes forming a cavity on a substrate where the cavity has a cavity profile that is configured to accept an emitter pixel structure for an LED, forming at least one passivation layer in the cavity, and forming at least one optical layer in the cavity on at least a portion of one of the at least one passivation layer. The at least one optical layer is configured to increase a lumen output of the emitter pixel structure. The method further includes forming the emitter pixel structure in the cavity on the at least one optical layer of the emitter pixel structure where the cavity profile is configured to adjust an emitted light wavelength of the emitter pixel structure.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

Abstract: The present technology relates to an electromagnetic wave processing device that enables suppression of a ripple. Provided are a photoelectric conversion element, a narrow band filter stacked on a light incident surface side of the photoelectric conversion element and configured to transmit an electromagnetic wave having a desired wavelength, and interlayer films respectively formed above and below the narrow band filter, and the narrow band filter is formed in a shape with a level difference. The level difference is formed for each photoelectric conversion element. Alternatively, the level difference is formed between the photoelectric conversion elements and in the interlayer film. The present technology can be applied to an imaging element or a sensor using a plasmon filter or a Fabry-Perot interferometer.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

Abstract: Apparatuses with a gate electrode in a semiconductor device are described. An example apparatus includes an active region, an isolation region surrounding the active region, a dielectric layer including a first portion above the active region and a second portion above the isolation region, and a protection layer on the isolation region.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.

Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: An image sensor package may include a semiconductor wafer having a pixel array, a color filter array (CFA) formed over the pixel array, and one or more lenses formed over the CFA. A light block layer may couple over the semiconductor wafer around a perimeter of the lenses and an encapsulation layer may be coupled around the perimeter of the lenses and over the light block layer. The light block layer may form an opening providing access to the lenses. A mold compound layer may be coupled over the encapsulation layer and the light block layer. A temporary protection layer may be used to protect the one or more lenses from contamination during application of the mold compound and/or during processes occurring outside of a cleanroom environment.

Abstract: The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

Abstract: A method for forming a semiconductor arrangement is provided. The method includes forming a patterned photoresist over a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a gas comprising fluoride, wherein fluoride residue from the gas remains on the top surface of the substrate after removing the patterned photoresist. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.

Abstract: A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.