Patents Examined by Julio C Diaz Perez
  • Patent number: 8339141
    Abstract: A voltage pulse is transmitted into a test object, and returned reflection pulses are evaluated to determine the location of a fault in the test object. The return signal includes a reflection from the fault and undesired interfering reflection pulses, which are removed or compensated-out from the return signal to produce a corrected pulse diagram. A circuit arrangement for this includes a bi-directional coupler, a separation filter, a measured signal detection circuit with two input channels, a memory storing a database, a computer processor, and a measured signal evaluation unit. A method in this regard includes a first step of measuring the input impedance of the test object, and a second step of measuring the return signal pulses, transforming the return signal to the frequency domain, compensating the frequency domain data to remove interference, transforming the data back to the time domain, and representing or evaluating the pulse diagram.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: December 25, 2012
    Assignee: Hagenuk KMT Kabelmesstechnik GmbH
    Inventors: Patrick Gray, Hubert Schlapp
  • Patent number: 8305095
    Abstract: A voltage measurement device for connection to a primary voltage dividing element provided between ground and an electrically conducting element in a system for controlling an electrical process and such a system. The device includes at least one first branch of secondary voltage dividing elements, where the branch is adapted to be connected in parallel with the primary voltage dividing element, and a first measuring unit connected to one of the secondary voltage dividing elements of the first branch and arranged to measure the voltage across this secondary voltage dividing element and provide a first voltage signal corresponding to a voltage of the electrically conducting element.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: November 6, 2012
    Assignee: ABB Technology AG
    Inventors: Hans Björklund, Krister Nyberg
  • Patent number: 8241926
    Abstract: A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: August 14, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yasuhiro Yoshikawa