Patents Examined by Julio J. Maldonado
  • Patent number: 11107790
    Abstract: A laser bonding method includes forming a bonding part including an adhesive layer and a conductive particle disposed within the adhesive layer on a substrate; aligning a bonding target by disposing the bonding target on a surface of the bonding part opposite the substrate; disposing a pressing part on a surface of the bonding target that is opposite to the bonding part and pressing the bonding target onto the bonding part through the pressing part; heating the bonding target by irradiating at least the pressing part with a laser and conducting heat from the pressing part to the bonding target and from the bonding target to the bonding part; and bonding together the bonding part and the bonding target by the heat conducted from the bonding target to the bonding part so that the conductive particle electrically connects the substrate and the bonding target. The pressing part may be removed.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Seong Choi, Yong Sung Eom, KeonSoo Jang, Seok-Hwan Moon, Hyun-cheol Bae
  • Patent number: 11087993
    Abstract: Integrated chips and methods of forming the same include forming lines of alternating first and second sacrificial fills in a film. A dielectric cut is formed in at least one of the first sacrificial fills. A dielectric cut is formed in at least one of the second sacrificial fills. Remaining first and second sacrificial fill material is replaced with a conductive material. The film is replaced with a final dielectric material.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chih-Chao Yang, Kangguo Cheng, Hsueh-Chung Chen
  • Patent number: 11075269
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11069575
    Abstract: A semiconductor device and its manufacturing method are presented, relating to semiconductor technology. The manufacturing method comprises: providing a substrate structure comprising a substrate, a source region on the substrate, and a gate structure on the source region; forming cavities on two opposing sides of the gate structure; epitaxially growing electrodes in the cavities, with each electrode comprising an electrode body and an amorphous layer on the electrode body; forming an dielectric layer on the substrate structure covering the electrodes and the gate structure; etching the dielectric layer to form a contact hole exposing the amorphous layer; forming a conductive adhesive layer on the bottom and on the side of the contact hole; and forming a contact component on the conductive adhesive layer filling the contact hole. In this semiconductor device, the adhesive layer may be directly formed on the amorphous layer, resulting in improved performance of the device.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 20, 2021
    Inventor: Jiquan Liu
  • Patent number: 11018130
    Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: XILINX, INC.
    Inventor: Mohammed Fakhruddin
  • Patent number: 10985231
    Abstract: A display device includes a substrate, a plurality of active pixels, and a plurality of passive pixels. The substrate has a first display region and a second display region connected to the first display region. The plurality of passive pixels are disposed on the first display region. The plurality of active pixels are disposed on the second display region.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 20, 2021
    Assignee: Au Optronics Corporation
    Inventors: Peng-Yu Chen, Ya-Pei Kuo, Hong-Shiung Chen
  • Patent number: 10923600
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 10916690
    Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jerry M. Chow
  • Patent number: 10903427
    Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 26, 2021
    Assignee: eMagin Corporation
    Inventors: Munisamy Anandan, Amalkumar P. Ghosh
  • Patent number: 10896947
    Abstract: A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches that protrude from the connection wirings in a direction perpendicular to a direction in which the connection wirings are primarily extended.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minseong Yi, Seungmin Lee, Jungkyu Lee, Seunghwan Cho, Gyungsoon Park, Jaeun Lee
  • Patent number: 10886449
    Abstract: Disclosed herein is a semiconductor device package including: a body including a cavity; a semiconductor device disposed in the cavity; a light transmitting member disposed on the cavity; and an adhesive layer which fixes the light transmitting member to the body, wherein the cavity includes a stepped portion on which the light transmitting member is disposed, the stepped portion includes a first bottom surface and a third bottom surface spaced apart from each other in a first direction, a second bottom surface and a fourth bottom surface spaced apart from each other in a second direction perpendicular to the first direction, a first connecting portion in which the first bottom surface and the second bottom surface are connected to each other, a second connecting portion in which the second bottom surface and the third bottom surface are connected to each other, a third connecting portion in which the third bottom surface and the fourth bottom surface are connected to each other, and a fourth connecting porti
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Koh Eun Lee
  • Patent number: 10879425
    Abstract: A light-emitting device includes a package, at least one light-emitting element and a light-absorbing member. The package defines a recess having an opening at a light extraction surface of the package. A part of the recess is defined by an upward-facing surface of the package. The light-emitting element is mounted on the upward-facing surface of the package. The light-absorbing member is disposed in the recess, spaced apart from the light-emitting element, and having an exposed surface facing upward toward the light extraction surface, the exposed surface being exposed from the upward-facing surface of the package with the exposed surface and the upward-facing surface of the package being on the same plane.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 29, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takeo Kurimoto, Yuki Miyaura
  • Patent number: 10879116
    Abstract: A method and apparatus for processing a substrate are provided. In some implementations, the method comprises providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture, depositing a metal seed layer on the exposed silicon contact surface and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: December 29, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roman Gouk, Steven Verhaverbeke
  • Patent number: 10847452
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10833118
    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 10, 2020
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 10825858
    Abstract: In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 3, 2020
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Yasushi Tateshita, Kazunobu Ota
  • Patent number: 10825891
    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION ARMONK
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10741532
    Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10741650
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate. A rearmost portion of the first side surface is substantially perpendicular to the front surface.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Fujita, Takanobu Ono, Makoto Minaminaka
  • Patent number: 10727440
    Abstract: A display device includes a substrate including a display area and a peripheral area outside the display area, the peripheral area including a bendable bending region, a display member on the display area of the substrate to display an image, and a protection film under the substrate, the protection film including a groove at a position corresponding to the bending region of the peripheral area, wherein the groove includes a bottom surface and inner walls extending from the bottom surface to a surface of the protection film, a boundary part being defined at an intersection of each inner wall with the surface of the protection film, and wherein boundary parts adjacent to opposite ends of the protection film are separated from the opposite ends of the protection film, respectively.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoung Yong Kim, Jeong Ho Hwang