Patents Examined by Julio J. Maldonado
  • Patent number: 10276450
    Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Tong Lei, Yongyue Chen, Haifeng Zhou
  • Patent number: 10249822
    Abstract: Provided is a polymer blend for a semiconducting layer of an organic electronic device, comprising: a first polymer; a second polymer which is different from the first polymer; and a semiconductor compound selected from the group of pentacene derivatives and thiophene derivatives. The semiconductor compound is distributed homogeneously in the semiconducting layer in the direction parallel to the surface of the electrodes. This improved lateral distribution of the semiconductor compound in the semiconducting layer provides a reduced contact resistance, particularly for short channel length devices.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 2, 2019
    Assignees: Cambridge Display Technology Limited, Sumitomo Chemical Company Limited
    Inventors: Christopher Newsome, Shuji Doi
  • Patent number: 10243132
    Abstract: Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sami Rosenblatt, Markus Brink, Rasit Onur Topaloglu
  • Patent number: 10242910
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 26, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
  • Patent number: 10236459
    Abstract: Disclosed is a display device including: a display panel 40 including an element substrate 20 having a first resin substrate 10a over which a first underlayer film 11a and a plurality of switching elements are provided, and a counter substrate 30 having a second resin substrate 10b on which a second underlayer film 11b is provided; and a functional sheet 45 bonded to a surface, of the display panel 40, close to the counter substrate 30. The display device has a curved portion C in which the display panel 40 is able to be curved at a predetermined radius of curvature, and a pair of flat portions between which the curved portion C is interposed and a predetermined angle is formed, and in which the display panel 40 is held flatly. The functional sheet 45 is bonded such that the curved portion C is able to be maintained at the predetermined radius of curvature.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 19, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Hasegawa, Yuki Yasuda, Takashi Ochi, Hiroshi Sugimoto, Shoji Okazaki, Kenji Misono
  • Patent number: 10224454
    Abstract: Group III nitride based light emitting diode (LED) structures include multiple quantum wells with barrier-well units that include III nitride interface layers. Each interface layer may have a thickness of no greater than about 30% of an adjacent well layer, and a comparatively low concentration of indium or aluminum. One or more interface layers may be present in a barrier-well unit. Multiple barrier-well units having different properties may be provided in a single active region.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: March 5, 2019
    Assignee: Cree, Inc.
    Inventors: Thomas A. Kuhr, Robert David Schmidt, Daniel Carleton Driscoll, Brian T. Collins
  • Patent number: 10221272
    Abstract: A method of forming a patterned polymer layer on a substrate and a substrate having a polymer layer formed by the method. The method includes providing a substrate comprising a first surface having a first surface energy and a pattern located on the substrate forming a second surface having a second, lower surface energy than the first surface, and selectively depositing a polymeric layer onto the first surface using a monomer material in an initiated chemical vapor deposition process, wherein the initiated chemical vapor deposition process is operated under supersaturation conditions during the deposition process.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 5, 2019
    Assignee: DREXEL UNIVERSITY
    Inventors: Kenneth Ka Shun Lau, Sruthi Janakiraman, Chia-Yun Hsieh
  • Patent number: 10204988
    Abstract: An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 12, 2019
    Assignee: Nokia Technologies Oy
    Inventor: Michael Astley
  • Patent number: 10192791
    Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman, Charlotte Adams, Jinping Liu, Keith Tabakman
  • Patent number: 10181422
    Abstract: The present disclosure belongs to the field of display and discloses an array substrate and a method for manufacturing the same, and a display apparatus. The array substrate comprises a first signal line and a second signal line provided side by side in a same direction and in a same layer, the second signal line comprising two separated parts, and a separation region being provided between the two separated parts; a first lead, configured to be connected to the first signal line, and pass through the separation region, so as to intersect with the second signal line; and a second lead, configured to be in a layer different than that of the second signal line, and conned the two separated parts.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shaoru Li, Rui Wang, Ni Yang, Shuai Chen
  • Patent number: 10177079
    Abstract: A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: January 8, 2019
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Hideo Nishikubo, Shunji Masumori, Takuya Harada, Tomohiro Ishii, Hidemichi Fujiwara
  • Patent number: 10176984
    Abstract: Methods and apparatuses for selectively depositing silicon oxide on a silicon oxide surface relative to a silicon nitride surface are described herein. Methods involve pre-treating a substrate surface using ammonia and/or nitrogen plasma and selectively depositing silicon oxide on a silicon oxide surface using alternating pulses of an aminosilane silicon precursor and an oxidizing agent in a thermal atomic layer deposition reaction without depositing silicon oxide on an exposed silicon nitride surface.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 8, 2019
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Dennis M. Hausmann
  • Patent number: 10158099
    Abstract: Organic light-emitting device manufacturing method performed by using a manufacturing apparatus placed where light from outside is blocked and a lighting device emitting light constituted of light components with wavelengths of 500 nm or longer is placed. The manufacturing apparatus includes a main body having an ejector ejecting ink containing organic light-emitting material and a light-transmissive tube forming at least part of a transport path connecting a tank containing the ink and the ejector. The method includes: removing the ink inside the transport path when a total exposure amount ET (lux×hours) satisfies ET??×17500 where ? is a constant satisfying ??1. ET is a product of E denoting light amount (lux) from the lighting device to which the tube is exposed and T denoting time amount (hours) over which the tube is exposed to the light from the lighting device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 18, 2018
    Assignees: JOLED INC., SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hirotaka Nanno, Masaki Nishimura, Masashi Komatsu, Sadamu Yoshida
  • Patent number: 10158014
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 18, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Ming-Han Liao, Minghwei Hong
  • Patent number: 10155369
    Abstract: The present disclosure relates to a method for debonding a pair of bonded substrates. In the method, a debonding apparatus is provided comprising a wafer chuck, a flex wafer assembly, and a set of separating blades. The pair of bonded substrates is placed upon the wafer chuck so that a first substrate of the bonded substrate pair is in contact with a chuck top surface. The flex wafer assembly is placed above the bonded substrate pair so that its first surface is in contact with an upper surface of a second substrate of the bonded substrate pair. A pair of separating blades having different thicknesses is inserted between the first and second substrates from edges of the pair of bonded substrates diametrically opposite to each other while the second substrate is concurrently pulled upward until the flex wafer assembly flexes the second substrate from the first substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Patent number: 10158039
    Abstract: A semiconductor device is formed using an n-type layer of Zinc Oxide, a p-type layer formed of a narrow bandgap material. The narrow bandgap material uses a group 3A element and a group 5A element. A junction is formed between the n-type layer and the p-type layer, the junction being operable as a heterojunction diode having a rectifying property at a temperature range, the temperature range having a high limit at room temperature.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. De Souza, Yun Seog Lee, Ning Li, Devendra Sadana, Yao Yao
  • Patent number: 10153274
    Abstract: A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n+-type semiconductor region and the p+-type semiconductor region, and at least apart of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n+-type semiconductor region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Sadayuki Ohnishi
  • Patent number: 10153362
    Abstract: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10141456
    Abstract: The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 27, 2018
    Assignee: Fraunhofer Gesellschaft Zur Forderung Der Angew. Forschung E.V.
    Inventors: Andreas Hürner, Tobias Erlbacher
  • Patent number: 10141200
    Abstract: In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Mun Byun, Badro Im, Hong-Rae Kim, Sin-Hae Do, Gyeong-Deok Park