Patents Examined by Julio J. Maldonado
  • Patent number: 11557530
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 17, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har Khor, Tian Hing Lim, Hui Min Ler, Chee Hiong Chew, Phillip Celaya
  • Patent number: 11545483
    Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 3, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xia Li, Haining Yang, Bin Yang
  • Patent number: 11545549
    Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: January 3, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Steven M. Shank, Siva P. Adusumilli, Yves Ngu, Michael Zierak
  • Patent number: 11508882
    Abstract: Disclosed in the present application are a quantum dot LED, a manufacturing method thereof, and a display device, belonging to the technical field of LED light sources. The quantum dot LED includes an LED support, an LED chip, a filling layer, and a quantum dot layer, where the LED support comprises a chamber; the LED chip is arranged on a bottom surface of the chamber; the filling layer covers the bottom surface of the chamber and the LED chip, and is engaged with walls of the chamber; and the quantum dot layer is arranged at an opening on a top surface of the chamber, a light incident side of the quantum dot layer abuts against a surface of the filling layer away from the bottom surface of the chamber, and a shortest distance h between the LED chip and the quantum dot layer meets h?0.03 mm.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 22, 2022
    Assignee: Hisense Visual Technology Co., Ltd.
    Inventors: Fulin Li, Zhicheng Song
  • Patent number: 11502168
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Wei Hsu, Hou-Yu Chen, Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang, Jia-Ni Yu, Lung-Kun Chu
  • Patent number: 11495690
    Abstract: A semiconductor device having high on-state current and high reliability is provided. The semiconductor device includes, a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor and a second conductor over the second oxide; a third oxide over the second oxide; a second insulator over the third oxide; a third conductor located over the second insulator and overlapping with the third oxide; a third insulator in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; a fourth insulator over the third insulator; a fifth insulator over the fourth insulator; and a sixth insulator over the third conductor, the second insulator, the third oxide and the fifth insulator.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Katsuaki Tochibayashi, Ryota Hodo
  • Patent number: 11494543
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11495597
    Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 8, 2022
    Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
  • Patent number: 11488960
    Abstract: The present application discloses a semiconductor device with a tapering impurity region and the method for fabricating the semiconductor device with the tapering impurity region. The semiconductor device includes a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11488920
    Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ?3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 1, 2022
    Assignee: AG MATERIALS TECHNOLOGY CO., LTD.
    Inventors: Hsing-Hua Tsai, An-Chi Chuang, Po-Ching Wu, Chung-Hsin Chou
  • Patent number: 11482671
    Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 25, 2022
    Assignee: eMagin Corporation
    Inventors: Munisamy Anandan, Amalkumar P. Ghosh
  • Patent number: 11482426
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: October 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 11476436
    Abstract: An organic light-emitting display apparatus and a manufacturing method thereof have improved process stability and reliability by reducing damage to the organic light-emitting display apparatus during a manufacturing process. The organic light-emitting display apparatus includes: a substrate, a plurality of pixel electrodes, a pixel defining film, a plurality of hole control layers respectively arranged on the pixel electrodes, a plurality of emission layers respectively arranged on the hole control layers, a plurality of buffer layers respectively arranged on the emission layers, each of the buffer layers having a highest occupied molecular orbital (HOMO) energy level greater than the HOMO energy level of each of the plurality of emission layers, and an opposite electrode integrally provided over the buffer layers.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 18, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaeik Kim, Jaesik Kim, Yeonhwa Lee, Joongu Lee, Sehoon Jeong, Jiyoung Choung
  • Patent number: 11476113
    Abstract: There is provided a technique having a process that includes forming a film, which contains a first element and a second element on a substrate by performing a cycle a predetermined number of times, the cycle sequentially performing: (a) supplying a first precursor gas containing the first element to the substrate in a process chamber; (b) supplying a second precursor gas, which contains the first element and has a pyrolysis temperature lower than a pyrolysis temperature of the first precursor gas, to the substrate; and (c) supplying a reaction gas, which contains the second element that is different from the first element, to the substrate.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 18, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Ryota Kataoka, Hiroaki Hiramatsu, Kiyohisa Ishibashi
  • Patent number: 11476223
    Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daisuke Koike, Fumiyoshi Kawashiro
  • Patent number: 11476108
    Abstract: A method of manufacturing a semiconductor device includes forming a spin on carbon layer comprising a spin on carbon composition over a semiconductor substrate. The spin on carbon layer is first heated at a first temperature to partially crosslink the spin on carbon layer. The spin on carbon layer is second heated at a second temperature to further crosslink the spin on carbon layer. An overlayer is formed over the spin on carbon layer. The second temperature is higher than the first temperature.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing Hong Huang, Ching-Yu Chang, Wei-Han Lai
  • Patent number: 11462482
    Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer, an unevenness-absorptive resin layer, and an adhesive resin layer in this order and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component such that the circuit forming surface is protected; and a step of forming an electromagnetic wave-shielding layer on the electronic component in a state of being attached to the adhesive laminated film.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 4, 2022
    Assignee: MITSUI CHEMICALS TEHCELLO, INC.
    Inventors: Takashi Unezaki, Jun Kamada, Akimitsu Morimoto, Jin Kinoshita
  • Patent number: 11456213
    Abstract: There is provided a processing method of a wafer having a functional layer on a front surface side. The processing method includes a laser processing step of forming laser processed grooves along streets while removing the functional layer along the streets by executing irradiation with a laser beam and a cut groove forming step of forming cut grooves inside the laser processed grooves along the streets by cutting the wafer by a cutting blade. The processing method also includes a grinding step of causing the cut grooves to be exposed on a back surface side of the wafer and dividing the wafer into plural device chips by grinding the back surface side of the wafer and thinning the wafer and a processing distortion removal step of supplying a gas in a plasma state to the back surface side of the wafer and removing processing distortion.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 27, 2022
    Assignee: DISCO CORPORATION
    Inventors: Yoshiteru Nishida, Hidekazu Iida, Kenta Chito
  • Patent number: 11456389
    Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.
    Type: Grant
    Filed: July 26, 2020
    Date of Patent: September 27, 2022
    Assignee: Champion Microelectronic Corp.
    Inventors: Haiping Dun, Hung-Chen Lin
  • Patent number: 11450715
    Abstract: A display device includes a base substrate, a plurality of display elements, a first light control layer, and a second light control layer. The base substrate includes a pixel region and a peripheral region adjacent to the pixel region. The display elements are disposed on the base substrate, overlap the pixel region in a plan view, and are configured to generate a first light. The first light control layer is disposed on the display elements, and includes a transmission part configured to transmit the first light, a first light conversion part configured to convert the first light into a second light, and a second light conversion part configured to convert the first light into a third light. The second light control layer overlaps at least a portion of the first light conversion part in the plan view and is configured to convert the first light into the second light.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: September 20, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soodong Kim, YongSeok Choi, Sujin Kim, Woo-Man Ji, Hoyeon Ji