Patents Examined by Julio J. Maldonado
  • Patent number: 10727170
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har Khor, Tian Hing Lim, Hui Min Ler, Chee Hiong Chew, Phillip Celaya
  • Patent number: 10727440
    Abstract: A display device includes a substrate including a display area and a peripheral area outside the display area, the peripheral area including a bendable bending region, a display member on the display area of the substrate to display an image, and a protection film under the substrate, the protection film including a groove at a position corresponding to the bending region of the peripheral area, wherein the groove includes a bottom surface and inner walls extending from the bottom surface to a surface of the protection film, a boundary part being defined at an intersection of each inner wall with the surface of the protection film, and wherein boundary parts adjacent to opposite ends of the protection film are separated from the opposite ends of the protection film, respectively.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoung Yong Kim, Jeong Ho Hwang
  • Patent number: 10717645
    Abstract: A method of encapsulating a sensor device includes providing at least one sensor device that has a sensor portion on a substrate. An exclusionary zone is formed above an upper surface of the sensor portion. An outer boundary is formed on or about the sensor device with the outer boundary encircling the exclusionary zone. A mold material is deposited into a volume defined in part by the sensor device, the exclusionary zone, and the outer boundary to encapsulate portions of the sensor device. The exclusionary zone in one embodiment is an inner boundary that is formed on the sensor portion. The inner boundary encircles a portion of the upper surface of the sensor portion. The exclusionary zone in another embodiment is a selectively removable material deposited on the upper surface of the sensor portion. The selectively removable material occupies a space above a portion of the upper surface.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 21, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Ando Feyh, Gary O'Brien
  • Patent number: 10714425
    Abstract: In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventor: Sanjay Dabral
  • Patent number: 10700059
    Abstract: In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10672605
    Abstract: A technique regarding film formation capable of forming a three-dimensional pattern successfully is provided. A film forming method for a processing target object is provided. The processing target object has a supporting base body and a processing target layer. The processing target layer is provided on a main surface of the supporting base body and includes protrusion regions. Each protrusion region is extended upwards from the main surface, and an end surface of each protrusion region is exposed when viewed from above the main surface. The film forming method includes a first process of forming a film on the end surface of each protrusion region; and a second process of selectively exposing one or more end surfaces by anisotropically etching the film formed through the first process.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Masahiro Tabata
  • Patent number: 10665763
    Abstract: An equipment system for bond-packaging an LED using a thermoplastic resin photoconverter by rolling includes: a cooperative roll-shaping and roll-cutting apparatus used for performing roll-shaping and roll-cutting on a photoconversion sheet, to form a photoconversion sheet array; and a roll-bonding apparatus used for performing roll-bonding on the photoconversion sheet array and a flip chip LED array. The cooperative roll-shaping and roll-cutting apparatus and the roll-bonding apparatus are arranged sequentially to form cooperatively linked process equipment, where the cooperative roll-shaping and roll-cutting apparatus includes a first rolling device with a protrusion array and a second rolling device with a recess array that are disposed face-to-face and aligned with each other, and the roll-bonding apparatus includes a fourth rolling device with a recess array and a third rolling device with a smooth rolling surface that are disposed face-to-face and aligned with each other.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 26, 2020
    Assignee: Jiangsu Cherrity Optronics Co., Ltd.
    Inventor: Jinhua He
  • Patent number: 10658495
    Abstract: A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Sungjae Lee
  • Patent number: 10644099
    Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert V. Seidel, Thomas G. McKay, Tibor Bolom
  • Patent number: 10636908
    Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
  • Patent number: 10622257
    Abstract: The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Zuoguang Liu
  • Patent number: 10620487
    Abstract: The present disclosure provides a pixel structure, an array substrate and a display device and a method for manufacturing the same. The pixel structure includes a pixel electrode layer and signal lines. The pixel electrode layer is divided into a plurality of domain display areas. Each domain display area includes a plurality of bar-like electrodes which extend with a given angle. The signal lines are in a layer different from the pixel electrode layer. Dividing lines of at least a part of the domain display areas in the pixel electrode layer are in areas covered by the signal lines.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 14, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolin Wang, Hui Zhang, Li Xiao
  • Patent number: 10608143
    Abstract: A light-emitting component is disclosed. In an embodiment the light-emitting device includes a first layer stack for generating light, at least one additional layer stack for generating light, wherein each of the first layer stack and the at least one additional layer stack are separately drivable from one another and an auxiliary structure arranged between the first layer stacks and the at least one additional layer stacks.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 31, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Daniel Riedel, Andreas Rausch, Ulrich Niedermeier
  • Patent number: 10600879
    Abstract: A trench structure is located directly laterally between a first well and a first source region for a first transistor and the second well region with a second source for a second transistor. The trench structure includes a first gate structure for the first transistor, a second gate structure for the second transistor, a first conductive field plate structure, and a second conductive field plate structure. The first gate structure, the first field plate structure, the second field plate structure, and the second gate structure are located in the trench structure in a lateral line between the first well region and the second well region. The trench structure includes a dielectric separating the first field plate structure and the second field plate structure from each other in the lateral line. A drain region for the first transistor and the second transistor includes a portion located directly below the trench structure.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Bernhard Grote, Saumitra Raj Mehrotra, Ljubo Radic, Vishnu Khemka
  • Patent number: 10553450
    Abstract: A method for thermally processing a minimally absorbing thin film in a selective manner is disclosed. Two closely spaced absorbing traces are patterned in thermal contact with the thin film. A pulsed radiant source is used to heat the two absorbing traces, and the thin film is thermally processed via conduction between the two absorbing traces. This method can be utilized to fabricate a thin film transistor (TFT) in which the thin film is a semiconductor and the absorbers are the source and the drain of the TFT.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 4, 2020
    Assignee: NCC NANO, LLC
    Inventors: Kurt A. Schroder, Robert P. Wenz
  • Patent number: 10501311
    Abstract: A micromechanical device having a first cavity, which has a MEMS element, and having a second cavity. The second cavity is connected to the first cavity with a connection channel, the connection channel having a seal by which the first cavity and the second cavity are hermetically sealed from each other, the seal being able to be opened electrically.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 10, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Martin Rambach
  • Patent number: 10504858
    Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Hao-Cheng Hou, Jung-Wei Cheng
  • Patent number: 10475663
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5exp(5.4×103tN-)??expression 1 ?: the lifetime of carriers in the drift layer tN-: the layer thickness of the drift layer.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10475759
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 10475791
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey