Patents Examined by Julio J. Maldonado
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 11908829
    Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng
  • Patent number: 11901406
    Abstract: A semiconductor device comprises a substrate, a semiconductor layer formed on the substrate; and a high-voltage termination. The high-voltage termination includes a plurality of floating field rings, a deep trench and a dielectric material is disposed within the deep trench. The plurality of floating field rings are formed in the semiconductor layer and respectively disposed around a region of the semiconductor layer. The deep trench is formed in the semiconductor layer and concentrically disposed around an outermost floating field ring of the plurality of floating field rings. The high-voltage termination may also include a field plate disposed over the floating field rings, the deep trench, or both.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: February 13, 2024
    Assignee: Analog Power Conversion LLC
    Inventors: Amaury Gendron-Hansen, Dumitru Gheorge Sdrulla
  • Patent number: 11887921
    Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 30, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics SDN BHD
    Inventors: Andrea Albertinetti, Marifi Corregidor Cagud
  • Patent number: 11887864
    Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 30, 2024
    Assignee: Microchip Technology Incorporated
    Inventors: Wichai Kovitsophon, Rangsun Kitnarong, Ekgachai Kenganantanon, Pattarapon Poolsup, Watcharapong Nokde, Chanyuth Junjuewong
  • Patent number: 11886078
    Abstract: The method of manufacturing a light emitting module includes: providing a light guiding plate having a first main surface serving as a light emitting surface; and a second main surface positioned opposite to the first main surface and provided with a recess; providing a light adjustment portion containing a fluorescent material; providing a light emitting element unit in which a light emitting element comprising an electrode is integrally bonded to the light adjustment portion; bonding the light adjustment portion of the light emitting element unit to the recess; and forming wiring on the electrode of the light emitting element.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 30, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Toru Hashimoto
  • Patent number: 11889685
    Abstract: A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11888060
    Abstract: A MOSFET device die includes an active area formed on a semiconductor substrate. The active area includes a first active area portion and a second active area portion. At least one mesa is formed in the semiconductor substrate extending in a longitudinal direction through the active area. The at least one mesa includes a channel region extending in a longitudinal direction. The channel region includes low threshold voltage channel portions and high threshold voltage channel portions. The first active area portion includes the channel portions in a first ratio of low threshold voltage channel portions to high threshold voltage channel portions, and the second active area portion includes channel portions in a second ratio of low threshold voltage channel portions to high threshold voltage channel portions. The first ratio is larger than the second ratio.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 30, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Prasad Venkatraman
  • Patent number: 11871562
    Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Erxuan Ping, Zhen Zhou, Lingguo Zhang, Weiping Bai
  • Patent number: 11862598
    Abstract: There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: January 2, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhiko Yoshihara
  • Patent number: 11855071
    Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yu Yang, Po-Wei Liu
  • Patent number: 11854997
    Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11854805
    Abstract: A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: December 26, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joël Kanyandekwe, Cyrille Le Royer
  • Patent number: 11855212
    Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: December 26, 2023
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Zhonghua Li, Runling Li, Nan Li, Jianghua Leng, Tianpeng Guan
  • Patent number: 11848349
    Abstract: A method of forming a curved semiconductor includes: forming a device layer on a semiconductor substrate; forming a metal layer on the device layer; removing the semiconductor substrate from the device layer; and curving the device layer and the metal layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 19, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Andrew C. Keefe, Geoffrey P. McKnight, Alexander R. Gurga, Ryan Freeman
  • Patent number: 11823889
    Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 11823924
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a reformer configured to partially reform a first substrate to form a reformed layer between a first portion and a second portion in the first substrate. The apparatus further includes a joiner configured to form a joining layer between the first portion and a second substrate to join the first portion and the second substrate. The apparatus further includes a remover configured to remove the second portion from a surface of the second substrate while making the first portion remain on the surface of the second substrate by separating the first portion and the second portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Aoi Suzuki
  • Patent number: 11823985
    Abstract: A leadframe includes a first frame part and a second frame part. The first frame part includes a bed portion including a first section being thin in a first direction, a first support portion, a first lead portion positioned between the bed portion and the first support portion in a second direction, the first lead portion being connected with the bed portion and the first support portion, a first extension portion being connected to the bed portion, and a second extension portion separated from the first extension portion in a third direction and connected to the bed portion. The second frame part includes a second support portion connected to the first and second extension portions, and a second lead portion connected to the second support portion.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: November 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Koji Araki
  • Patent number: 11817346
    Abstract: An isolator includes a first insulating portion, a first electrode provided in the first insulating portion, a second insulating portion provided on the first insulating portion and the first electrode, a third insulating portion provided on the second insulating portion, and a second electrode provided in the third insulating portion. The second insulating portion includes a plurality of first voids and a second void. The plurality of first voids are arranged in a first direction parallel to an interface between the first insulating portion and the second insulating portion. At least one of the first voids is provided under the second void.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 14, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Akira Ishiguro
  • Patent number: 11817323
    Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou