Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

Abstract: Provided is a technique suitable for multilayering thin semiconductor elements via adhesive bonding while avoiding wafer damage in a method of manufacturing a semiconductor device, the method in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method of the present invention includes bonding and removing. In the bonding step, a back surface 1b side of a thinned wafer 1T in a reinforced wafer 1R having a laminated structure including a supporting substrate S, a temporary adhesive layer 2, and the thinned wafer 1T is bonded via an adhesive to an element forming surface 3a of a wafer 3. A temporary adhesive for forming the temporary adhesive layer 2 contains a polyvalent vinyl ether compound, a compound having two or more hydroxy groups or carboxy groups and thus capable of forming a polymer with the polyvalent vinyl ether compound, and a thermoplastic resin.

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

Abstract: Devices having multiple multicomponent emissive layers are provided, where each multicomponent EML includes at least three components. Each of the components in each EML is a host material or an emitter. The devices have improved color stability and relatively high luminance.

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/?30 ?m at the first side of the power module.

Abstract: In one example, an electroplating system comprises a first bath reservoir, a second bath reservoir, a clamp, a first anode in the first bath reservoir, a second anode in the second bath reservoir, and a direct current power supply. The first bath reservoir contains a first electrolyte solution that includes an alkaline copper-complexed solution. The second bath reservoir contains a second electrolyte solution that includes an acidic copper plating solution. The direct current power supply generates a first direct current between the clamp and the first anode to electroplate a first copper layer on the cobalt layer of the wafer submerged in the first electrolyte solution. The direct current power supply then generates a second direct current between the clamp and the second anode to electroplate a second copper layer on the first copper layer of the wafer submerged in the second electrolyte solution.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes loading a first wafer and a second wafer onto a bonding platform such that the second wafer overlies the first wafer. An alignment process is performed to align the second wafer over the first wafer by virtue of a plurality of wafer pins, where a plurality of first parameters are associated with the wafer pins during the alignment process. The second wafer is bonded to the first wafer. An overlay (OVL) measurement process is performed on the first wafer and the second wafer by virtue of the plurality of wafer pins, where a plurality of second parameters are associated with the wafer pins during the alignment process.

Abstract: Provided is a technique suitable for multilayering thin semiconductor elements via adhesive bonding while avoiding wafer damage in a method of manufacturing a semiconductor device, the method in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method of the present invention includes bonding and removing. In the bonding step, a back surface 1b side of a thinned wafer 1T in a reinforced wafer 1R having a laminated structure including a supporting substrate S, a temporary adhesive layer 2, and the thinned wafer 1T is bonded via an adhesive to an element forming surface 3a of a wafer 3. A temporary adhesive for forming the temporary adhesive layer 2 contains a polyvalent vinyl ether compound, a compound having two or more hydroxy groups or carboxy groups and thus capable of forming a polymer with the polyvalent vinyl ether compound, and a thermoplastic resin.

Abstract: An apparatus having a seal plate which includes rigid hard portions and one or more flexible soft portions located between the hard portions is used for bonding at least one semiconductor device onto a substrate that is supported on a platform. The seal plate is movable between a first position which is spaced from the substrate and a second position whereat a first side of the seal plate is configured to be in contact with the substrate. A diaphragm covers a second side of the seal plate opposite to the first side. A fluid pressure generator exerts a fluid pressure onto the diaphragm to actuate the diaphragm to compress the one or more soft portions to transmit a bonding force onto the at least one semiconductor device during bonding.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

Abstract: A device for detecting a chemical species, including a Geiger-mode avalanche diode, which includes a body of semiconductor material delimited by a front surface. The semiconductor body includes: a cathode region having a first type of conductivity, which forms the front surface; and an anode region having a second type of conductivity, which extends in the cathode region starting from the front surface. The detection device further includes: a sensitive structure arranged on the anode region and including at least one sensitive region, which has an electrical permittivity that depends upon the concentration of the chemical species; and a resistive region, arranged on the sensitive structure and electrically coupled to the anode region.

Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.

Abstract: A method for manufacturing logic device isolation in an embedded storage process, removing the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retaining the floating gate oxide layer; depositing acid etching silicon nitride; removing the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation; remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation.

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.