Patents Examined by Junghwa M. Im
  • Patent number: 8575746
    Abstract: A Chip on Flexible Printed Circuit (COF) type semiconductor package may include a flexible film, a semiconductor IC chip on the flexible film, and a heating pad on the flexible film.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Si-Hoon Lee, Sa-Yoon Kang, Kyoung-Sei Choi
  • Patent number: 8525322
    Abstract: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 3, 2013
    Inventors: Yong Woo Kim, Yong Suk Yoo
  • Patent number: 8525347
    Abstract: The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: September 3, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Harald Seidl
  • Patent number: 8519547
    Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Alfred Haimerl, Angela Kessler, Michael Bauer
  • Patent number: 8519512
    Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
  • Patent number: 8513800
    Abstract: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film. Then, an In alloy film is formed from the In alloy pellet by heating, melting, and then cooling the In alloy pellet. As a result, the semiconductor chip and a heat spreader are bonded via the metal film and the In alloy film.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takaki Kurita, Osamu Igawa
  • Patent number: 8502254
    Abstract: Disclosed is a group III nitride semiconductor light-emitting device which suppresses electric current concentration in a light-transmitting electrode and a semiconductor layer directly below an electrode to enhance light emission efficiency, suppresses light absorption in the electrode or light loss due to multiple reflection therein to enhance light extraction efficiency, and has superior external quantum efficiency and electric characteristics. A semiconductor layer (20), in which an n-type semiconductor layer (4), a light-emitting layer (5) and a p-type semiconductor layer (6) are sequentially layered, is formed on a single-crystal underlayer (3) which is formed on a substrate (11). A light-transmitting electrode (7) is formed on the p-type semiconductor layer (6). An insulation layer (15) is formed on at least a part of the p-type semiconductor layer (6), and the light-transmitting electrode (7) is formed to cover the insulation layer (15).
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: August 6, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Daisuke Hiraiwa, Hironao Shinohara
  • Patent number: 8492765
    Abstract: Provided is a display device that includes: a gate line disposed on a substrate, the gate line including a protruding gate electrode; a data line extending across the gate line, the data line having first and second segments spaced apart from each other; a semiconductor pattern overlapping with the gate electrode; a drain electrode that contacts a drain region of the semiconductor pattern and connects the first and second segments; a source electrode that contacts a source region of the semiconductor pattern; and a storage electrode overlapping with the data line.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok-Je Seong, Jisuk Lim
  • Patent number: 8481417
    Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8482135
    Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Albert Auburger, Jochen Dangelmaier, Josef Hirtreiter
  • Patent number: 8476773
    Abstract: An electrical structure including a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stephen Leslie Buchwalter, Bruce K. Furman, Peter A. Gruber, Jae-Woong Nah, Da-Yuan Shih
  • Patent number: 8459956
    Abstract: A turbine blade includes an airfoil and integral platform at the root thereof. The platform is contoured in elevation from a ridge to a trough, and is curved axially to complement the next adjacent curved platform.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: June 11, 2013
    Assignee: General Electric Company
    Inventors: Vidhu Shekhar Pandey, Ching-Pang Lee, Jan Christopher Schilling, Aspi Rustom Wadia, Brian David Keith, Jeffrey Donald Clements
  • Patent number: 8455283
    Abstract: The present invention provides an organic electronic element manufacturing method which provides a low manufacturing cost and excellent performance stability, and specifically an organic electronic element manufacturing method which provides a low manufacturing cost, and minimizes emission unevenness, lowering of emission efficiency and shortening of lifetime due to deterioration of gas barrier property of sealing. The organic electronic element manufacturing method is featured in that it comprises the steps of forming an organic electronic structure composed of a first electrode, at least one organic layer and a second electrode on a flexible substrate, and applying a flexible sealing substrate to the organic electronic structure, followed by heating treatment, wherein a heating temperature, at which the heating treatment is carried out, is less than Tg (glass transition temperature) of the substrate and not less than Tg of the sealing substrate.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 4, 2013
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Nobuaki Takahashi, Hiroaki Yamagishi
  • Patent number: 8450186
    Abstract: Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 28, 2013
    Assignee: Intel Corporation
    Inventors: Haisheng Rong, Ansheng Liu
  • Patent number: 8446012
    Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I. Bao
  • Patent number: 8445928
    Abstract: A light-emitting diode (LED) light source module is described, comprising: a heat conduction substrate, wherein a surface of the heat conduction substrate includes a plurality of recesses; a plurality of light-emitting diode chips respectively disposed in the recesses; an insulation layer disposed on the surface of the heat conduction substrate outside of the recesses; an electric conduction layer disposed on the insulation layer, wherein the light-emitting diode chips are electrically connected to the electric conduction layer; and an encapsulation layer covering the light-emitting diode chips, the electric conduction layer and the insulation layer.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 21, 2013
    Assignee: CHI MEI Lighting Technology Corp.
    Inventors: Shi-Ming Cheng, Wen-Liang Li, Chang-Hsin Chu, Hsing-Mao Wang
  • Patent number: 8445325
    Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: May 21, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 8432030
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 30, 2013
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea
  • Patent number: 8426293
    Abstract: It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
  • Patent number: 8421227
    Abstract: A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: April 16, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee