Patents Examined by Karen Kusumakar
  • Patent number: 11367613
    Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: June 21, 2022
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Viljami Pore, Ryoko Yamada, Antti Juhani Niskanen
  • Patent number: 11362090
    Abstract: A semiconductor device includes a buried logic conductor (BLC) CFET, the BLC CFET including: relative to a first direction, first and second active regions arranged in a stack according to CFET-type configuration; first and second contact structures correspondingly electrically coupled to the first active region; third and fourth contact structures correspondingly electrically coupled to the second active region; a first layer of metallization over the stack which includes alpha logic conductors configured for logic signals (alpha logic conductors), and power grid (PG) conductors, the alpha logic and PG conductors being non-overlapping of each other; and a layer of metallization below the stack which includes beta logic conductors which are non-overlapping of each other; and wherein, relative to a second direction, each of the alpha logic, PG and beta logic conductors at least partially overlap one or more of the first, second, third and fourth contact structures.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Pochun Wang, Chih-Liang Chen, Li-Chun Tien
  • Patent number: 11361961
    Abstract: Described herein is a technique capable of improving the controllability of firm thickness distribution. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber; a first and a second gas supply system; an exhaust system; and a controller for controlling the first and the second gas supply system and the exhaust system to form a film. The first gas supply system includes: a first and a second storage part; a first gas supply port for supplying a gas stored in the first storage part from an outer periphery toward a center of a substrate; and a second gas supply for supplying the gas stored in the second storage part from the outer periphery along a direction more inclined toward the outer periphery than a direction from the outer periphery toward the center of the substrate.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Kokusai Electric Corporation
    Inventors: Kazuyuki Okuda, Syuzo Sakurai, Yasuhiro Inokuchi, Masayoshi Minami
  • Patent number: 11355500
    Abstract: A static random access memory (SRAM) cell includes a semiconductor fin, a first gate structure, a second gate structure, an epitaxy structure, and a first fin sidewall structure. The first gate structure crosses the semiconductor fin to form a pull-down (PD) transistor. The second gate structure crosses the semiconductor fin to form a pull-gate (PG) transistor. The epitaxy structure is on the semiconductor fin and between the first and second gate structures. The first fin sidewall structure is on a first side of the epitaxy structure and between the first and second gate structures. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • Patent number: 11355486
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: June 7, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuki Mizutani, Masaaki Higashitani, James Kai
  • Patent number: 11355515
    Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 7, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
  • Patent number: 11355401
    Abstract: A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Veeraraghavan S. Basker, Junli Wang, Albert Chu
  • Patent number: 11355434
    Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seung Song, Kwang-Young Lee, Jonghyun Lee
  • Patent number: 11355516
    Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang, Han-Jong Chia, Chung-Te Lin
  • Patent number: 11348829
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 11348921
    Abstract: A semiconductor structure comprises a substrate and a fin extruding from the substrate along a first direction, wherein the fin comprises a first conductive type semiconductive layer over the substrate, a second conductive type semiconductive layer stacking over the first conductive type semiconductive layer along the first direction, and a dielectric layer sandwiched by the first conductive type semiconductive layer and the second conductive type semiconductive layer providing electrical isolation along the first direction between the first conductive type semiconductive layer and the second conductive type semiconductive layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Wei-Lun Chen
  • Patent number: 11348840
    Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Liu, Hsueh-Chang Sung, Yee-Chia Yeo
  • Patent number: 11349014
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Patent number: 11342222
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang
  • Patent number: 11342219
    Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Kang Fu, Ming-Han Lee
  • Patent number: 11342361
    Abstract: A display device includes a substrate including a pixel area and a peripheral area located outside the pixel area; pixels located in the pixel area; power supply lines configured to provide an operating power to the pixels; and a plurality of data fanout wires configured to provide data signals to the pixels, wherein, in at least a portion of the peripheral area, the power supply lines and the plurality of data fanout wires are arranged on a same layer.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yang Wan Kim, Sun Ja Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee
  • Patent number: 11342383
    Abstract: The present disclosure provides a display panel and a display terminal, the display panel including an array substrate, a display device layer, and a color filter layer, wherein the display device layer includes a plurality of sub-pixel cycle units continuously arranged, and the sub-pixel cycle unit includes a plurality of sub-pixels. A part of sub-pixels is covered with the color resistors having colors corresponding to that of the sub-pixels to increase the color gamut of the sub-pixels, and meanwhile, sub-pixels not covered by the color resistors are used to increase brightness of the sub-pixels, thereby reducing the power consumption of the display panel, and improving a service life of the display panel, while improving a color gamut of the display panel.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: May 24, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Aiguo Tu
  • Patent number: 11342328
    Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guyoung Cho, Subin Shin, Donghyun Roh, Byung-Suk Jung, Sangjin Hyun
  • Patent number: 11342327
    Abstract: An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Abhishek A. Sharma, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 11342347
    Abstract: In-process source-level material layers including a source-level sacrificial layer is formed over a substrate, and an alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory openings and backside openings are formed through the alternating stack and into the in-process source-level material layers. Memory opening fill structures are formed in the memory openings. A source cavity is formed by removing the source-level sacrificial layer by introducing an etchant through the backside openings, and a source contact layer in the source cavity. The backside openings are laterally expanded and are merged to form backside trenches. Remaining portions of the sacrificial material layers are replaced with electrically conductive layers through the respective backside trenches.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 24, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Tatsuya Hinoue