Patents Examined by Karen Kusumakar
  • Patent number: 11004867
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A FeRAM (ferroelectric random access memory) device is arranged over the substrate between the first doped region and the second doped region. The FeRAM device has a ferroelectric material and a conductive electrode. The ferroelectric material is arranged over the substrate and the conductive electrode is arranged over the ferroelectric material and between sidewalls of the ferroelectric material.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Pai Chi Chou
  • Patent number: 10998275
    Abstract: An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Kyle Yazzie, Mohit Mamodia
  • Patent number: 10991881
    Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 27, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Steven Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison, Eduard A. Cartier, Vijay Narayanan, Marinus J. P. Hopstaken
  • Patent number: 10993330
    Abstract: The present disclosure relates to a display panel and a method of fabricating the same, and a display device. A display panel is provided which comprises: a display substrate having a first face and a second face opposite to the first face, the display substrate including a display area and a non-display area in the first face; a Chip-On-Film (COF) component disposed on the second face, the Chip-On-Film component comprising a COF film and an integrated circuit (IC) chip on the COF film; a connection hole located in the non-display area and at least penetrating the display substrate and the COF film; and an electrical connector disposed in the connection hole and electrically connecting the display substrate and the Chip-On-Film component.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 27, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiangdan Dong, Youngyik Ko, Ming Hu, Tingliang Liu
  • Patent number: 10985168
    Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jung-Chun Yen, Chien-Chih Wang, Guang Yang, Jiawei Lyu, Linshan Yuan, Wen Yi Tan
  • Patent number: 10985073
    Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Wenyu Xu, Brent Alan Anderson, Zuoguang Liu
  • Patent number: 10978338
    Abstract: A semiconductor device includes substrate, arrays, conductive structures, and liner spacer layer is provided. The substrate has array region and peripheral region. The arrays are disposed on the array region, and have conductive pillars. The conductive structures are located on the peripheral region, and have at least one connecting sidewall. The liner spacer layer covers the conductive pillars and the conductive structures. Sidewalls of the conductive pillars of the arrays facing a first direction and the connecting sidewall of the conductive structure are free from the liner spacer layer. The conductive pillars are arranged along a second direction in the array, and the second direction is different from the first direction. The liner spacer layer covering the arrays and the conductive structures are extended from the substrate. A manufacturing method of the semiconductor device is also provided.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10978523
    Abstract: An OLED display panel may include a substrate, an OLED light emitter on the substrate and configured to emit light, and a visible light sensor on the substrate and configured to detect at least a portion of the emitted light based on reflection of the portion of the emitted light from a recognition target. The visible light sensor is in a non-light emitting region adjacent to the OLED light emitter so as to be horizontally aligned with the OLED light emitter in a horizontal direction extending parallel to an upper surface of the substrate, or between the substrate and a non-light emitting region adjacent to the OLED light emitter such that the visible light sensor is vertically aligned with the non-light emitting region in a vertical direction extending perpendicular to the upper surface of the substrate.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Bae Park, Sung Young Yun, Gae Hwang Lee, Yong Wan Jin, Chul Joon Heo
  • Patent number: 10978294
    Abstract: Provided is a semi-insulating crystal represented by a composition formula InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), wherein each concentration of Si, B, and Fe in the crystal is less than 1×1015 at/cm3, electric resistivity under a temperature condition of 20° C. or more and 200° C. or less is 1×106 ?cm or more.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: April 13, 2021
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 10978298
    Abstract: Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 ?m, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100° C. to 2,500° C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Global Graphene Group, Inc.
    Inventor: Bor Z. Jang
  • Patent number: 10971461
    Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Ming-Chih Yew, Shin-Puu Jeng
  • Patent number: 10971478
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Aiping Tan
  • Patent number: 10971508
    Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Yao-Ting Tsai, Che-Fu Chuang, Jung-Ho Chang, Hsiu-Han Liao
  • Patent number: 10964656
    Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 30, 2021
    Assignee: NEPES CO., LTD.
    Inventors: Yong Tae Kwon, Hee Cheol Kim, Seung Jun Moon, Jini Shim
  • Patent number: 10964805
    Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, Naoya Okamoto
  • Patent number: 10957579
    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 23, 2021
    Inventors: Yung Bae Kim, Harsono Simka, Jong Hyun Lee
  • Patent number: 10950725
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Hsueh-Chang Sung
  • Patent number: 10950789
    Abstract: A resistive random access memory structure includes a semiconductor substrate, a transistor, a bottom electrode, a plurality of top electrodes, and a resistive-switching layer. The transistor is disposed over the semiconductor substrate. The bottom electrode is disposed over the semiconductor substrate and is electrically connected to a drain region of the transistor. The plurality of top electrodes is disposed along a sidewall of the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the plurality of top electrodes.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 16, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Bo-Lun Wu, Yi-Hsiu Chen, Ting-Ying Shen, Po-Yen Hsu
  • Patent number: 10950763
    Abstract: A method, comprising: providing a light emitting element including a semiconductor stack body and an electrode; providing a lightguide plate having a first surface and a second surface opposite to the first surface, wherein the second surface includes a plurality of recesses; arranging a light-transmitting member in each of the recesses; adjusting upper surfaces of the light-transmitting members to a uniform height; placing a wavelength conversion member on the light-transmitting member; placing the light emitting element on the wavelength conversion member with the electrode facing up; arranging a cover member that covers the light emitting element; removing the cover member until the electrode is exposed; and forming a wiring that electrically connects the light emitting elements together.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 16, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Shinichi Daikoku
  • Patent number: 10943919
    Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Taro Shiokawa, Masahisa Sonoda