Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area; forming a first active region in the first circuit area and a second active region on the second circuit area; forming first stacks with a first gate spacing on the first active region and second gate stacks with a second gate spacing on the second active region, the second gate spacing being different from the first gate spacing; performing an ion implantation to introduce a doping species to the first active region; performing an etching process, thereby recessing both first source/drain regions of the first active region with a first etch rate and second source/drain regions of the second active region; and epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

Abstract: A semiconductor device includes an interconnect including (i) a first layer, and (ii) a second layer provided on the first layer and including copper. The device also includes a plug provided on the interconnect and including (a) a third layer including titanium and nitrogen, and (b) a fourth layer provided on the third layer and including tungsten. A concentration of chlorine in the third layer is less than or equal to 5.0×1021 atoms/cm3, and a concentration of oxygen at the interface between the third layer and the fourth layer is less than or equal to 5.0×1021 atoms/cm3.

Abstract: A semiconductor device includes a first universal device formed over a substrate, an isolation structure over the first universal device, and a second universal device over the isolation structure. The first universal device includes a first source/drain (S/D) region formed over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region. The second universal device includes a third S/D region positioned over the isolation structure, a second channel region over the third S/D region, a fourth S/D region over the second channel region. The first universal device is one of a first n-type transistor according to first applied bias voltages, and a first p-type transistor according to second applied bias voltages. The second universal device is one of a second n-type transistor according to third applied bias voltages, and a second p-type transistor according to fourth applied bias voltages.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: A display device may include a hole, a display element, a switching element, a groove, a planarization layer, and a cover layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.

Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Abstract: Disclosed are a semiconductor structure and a forming method thereof.

Abstract: A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein the at least three sub-pixel include a first sub-pixel including a first conversion element, wherein the first conversion element includes a green phosphor, a second sub-pixel including a second conversion element, wherein the second conversion element includes a red phosphor and a third sub-pixel free of a conversion element, wherein the third sub-pixel is configured to emit blue primary radiation, wherein each sub-pixels has an edge length of at most 100 ?m, and wherein the pixel is a linear chain of sub-pixels and a plurality of pixels is arranged in a two dimensional ordered pattern so that a first sub-pixel is never adjacent to a third sub-pixel in a vertical direction and in a horizontal direction of the ordered pattern.

Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the conductive line and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A light emitting device includes: a substrate including a base member including an upper surface, a lower surface and one or more lateral surfaces, and defining a recess that is opened at the upper surface and the lateral surfaces and surrounds an outer perimeter of the upper surface; a first light emitting element; a second light emitting element; a light guide member covering the first and the second light emitting elements and the upper surface of the base member; and a first reflective member having a closed-ring shape surrounding the upper surface of the base member and the light guide member, a portion of the first reflective member being located in the recess. At least one of the lateral surfaces of the base member and corresponding at least one of one or more outer lateral surfaces of the first reflective member are in the same plane.