Patents Examined by Katharina Schuster
  • Patent number: 6389330
    Abstract: Combustion variables are diagnosed using sensors to measure turbulence in the post-flame zone as well as in the flame envelope of a combustor. Output signals from the sensors are processed and a set of statistical functions are calculated which are correlated with specific combustion variables, such as the concentration of unburned carbon in fly ash. A special sensor mounting box provides reliable long-term operation in harsh combustor environment, without a supply of cooling or protective air flow.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: May 14, 2002
    Assignee: Reuter-Stokes, Inc.
    Inventor: Mark J. Khesin
  • Patent number: 6336158
    Abstract: An input/output (I/O) decode arrangement including an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information useable for I/O address decoding for bus transaction ownership, for at least a portion of, and preferably all, possible I/O addresses in a system. Further included are: an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located; an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache. The I/O decode map can be located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: January 1, 2002
    Assignee: Intel Corporation
    Inventor: Andrew W. Martwick
  • Patent number: 6334161
    Abstract: A host computer logs in an image providing device such as a scanner connected by a serial bus, and reverses flow control of data transfer by issuing a Reverse command. The image providing device opens a transfer channel by an OpenChannel command, transfers image data in form of blocks. When the transfer of the image data has been completed, the image providing device closes the transfer channel by a CloseChannel command, and reverses the flow control of the data transfer again by the Reverse command. This changes the data transfer direction of a device having a bi-directional data transfer function, i.e., a device having a data reception function and a data providing function.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: December 25, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Naohisa Suzuki, Koji Fukunaga, Kiyoshi Katano, Jiro Tateyama, Atsushi Nakamura, Makoto Kobayashi
  • Patent number: 6332173
    Abstract: An asynchronous serial port provides automatic parity generation and detection in frames supporting address bits. In data frames comprising a variable number of data bits, the parity bit is located immediately following the last data bit and before the address bit. Parity generation is performed automatically based only on the preceding data bits. Parity detection allows interrupts to be generated directly from the parity bit received. Further, parity generation and detection is not dependent on the number of bits in the data frame.
    Type: Grant
    Filed: October 31, 1998
    Date of Patent: December 18, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Melanie D. Typaldos
  • Patent number: 6330627
    Abstract: Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: December 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 6327653
    Abstract: A technique for easily changing an operating system or working mode of a digital computer system includes: a CPU (central processing unit) for processing computer programs; a bus which transmits information to each system element by connecting elements to each other; a first memory connected to said bus, for temporarily storing system software and user software executed by the CPU; a second memory connected to said bus, for storing a system initialization program executed within the CPU; a backup memory which is connected to said bus and stores an operating system of a user by storing information of said first memory and system hardware; and a button detector for detecting operation of one of a plurality of buttons, each of said plurality of buttons corresponding to an operating system or working mode, said button detector providing an output to said central processing unit via said bus for causing the computer system to change operating systems or working modes in response thereto.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: December 4, 2001
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Sang-Jin Lee
  • Patent number: 6324601
    Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: November 27, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas P. Webber, Paul A. Wilcox
  • Patent number: 6324613
    Abstract: An apparatus and method which provide increased data flow through a compute platform by optimizing data flow between an external device and the internal circuitry without the need for user intervention. A port router is provided which includes a controller switch, a port switch, and one or more connections between the controller switch and the port switch. The controller switch, the port switch and the one or more connections are adapted to provide dynamic re-routing of connections between the port switch inputs and the controller switch outputs. A method is also provided for dynamically routing ports to internal circuitry of a compute platform.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: November 27, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Raul A. Aguilar, Kevin Joseph Lynch, James Thomas Clee, James Edward Guziak
  • Patent number: 6314475
    Abstract: A communication system for monitoring and/or controlling communication parameters of a communication device. The communication system monitors a communication channel that is created when the communication device connects to a network, controls the communication device as it operates on the network, and configures the communication device. The communication device is commonly a modem and is communicatively coupled to the network to carry out ongoing communications between the modem and the network through the communication channel. Further, a software module is associated with the modem, and the software module accesses the internal settings of the modem via the communication channel (if necessary) and performs operations such as monitoring, controlling, and configuring the modem (or other communication device) using the internal settings of the modem.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: November 6, 2001
    Assignee: Conexant Systems, Inc.
    Inventors: Zeev Collin, Tal Tamir
  • Patent number: 6311239
    Abstract: An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: October 30, 2001
    Assignee: Cypress Semiconductor Corp.
    Inventor: Joe P. Matthews
  • Patent number: 6308238
    Abstract: An adapter card for managing connections between clients and a network server off-loads the connection management burden from the server. The adapter card includes a memory with an embedded proxy application and a communication protocol stack, a processing unit for executing the application code, a network controller for interfacing with an internetwork, and a bus protocol bridge for interfacing with the internal bus of the network server. The proxy application receives client requests on behalf of the server over relatively slow and unreliable network connections, and submits the requests to the server over fast, reliable bus connections. Buffers are allocated to a particular client connection only after it is determined that data will be exchanged between the server and the client.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: October 23, 2001
    Assignee: Akamba Corporation
    Inventors: Jack J. Smith, Richard T. Burright, W. Spencer Worley, III, Eoin B. MacDonell, John A. Vastano, William T. Weatherford
  • Patent number: 6308274
    Abstract: A method and mechanism to enforce reduced access via restricted access tokens. Restricted access tokens are based on an existing token, and have less access than that existing token. A process is associated with a restricted token, and when the restricted process attempts to perform an action on a resource, a security mechanism compares the access token information with security information associated with the resource to grant or deny access. Application programs may have restriction information stored in association therewith, such that when launched, a restricted token is created for that application based on the restriction information thereby automatically reducing that application's access. Applications may be divided into different access levels such as privileged and non-privileged portions, thereby automatically restricting the actions a user can perform via that application.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: October 23, 2001
    Assignee: Microsoft Corporation
    Inventor: Michael M. Swift
  • Patent number: 6304936
    Abstract: A one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common storage system, and demultiplexer and control circuitry. The demultiplexer and control circuitry are configured so that cycle information destined for the first I/O bus interface is enqueued from the system bus interface into the first logical FIFO and is dequeued from the first logical FIFO into the first I/O bus interface. Cycle information destined for the second I/O bus interface is enqueued from the system bus interface into the second logical FIFO and is dequeued from the second logical FIFO into the second I/O bus interface. A level-of-fullness monitor monitors the common storage system and generates first and second level-of-fullness indications responsive thereto. The system bus interface is operable to declare I/O halt and I/O resume conditions on a system bus responsive to halt and resume commands.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: October 16, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Derek A. Sherlock
  • Patent number: 6298398
    Abstract: The present invention provides checking on information units sent and received as packets over fiber channel networks by providing check bits on the header information and separate check bits on the data.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: October 2, 2001
    Assignee: International Business Machines Corporation
    Inventors: Joseph C. Elliott, Daniel F. Casper, Louis W. Ricci, Brent C. Beardsley, Catherine C. Huang
  • Patent number: 6298399
    Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: October 2, 2001
    Assignee: Intel Corporation
    Inventor: Andrew Martwick
  • Patent number: 6289447
    Abstract: A method and apparatus for compensating system components based on system topology. The present invention provides a method and apparatus for performance optimization through topology dependent compensation. In one embodiment, one or more components of a computer system are coupled to a bus via self-compensated buffer(s). The self-compensated buffer(s) allow operating characteristics to be set via external signals such as voltage levels. System components have compensation units that receive external signals and configure the operating characteristics of the self-compensated buffer(s). In this manner a system designer may set operating characteristics for various system components based on the topology of the specific system rather than designing for a worst-case scenario.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: September 11, 2001
    Assignee: Intel Corporation
    Inventor: Alper Ilkbahar
  • Patent number: 6286055
    Abstract: There is here disclosed a movement error compensating device for a movable unit such as a slider in a numerical control machine tool. A laser beam is emitted from a reference position beam generator installed on a fixed base in the movement direction of the slider. The slider is provided with a beam passing position detector, which detects a deviation on YZ planes of the laser beam. In order to properly detect the irradiation direction of the laser beam, the fixed base is equipped with a movement end beam position detector.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: September 4, 2001
    Assignees: Okuma Corporation, Mitutoyo Corportion, Kabushiki Kaisha Mori Seiki Seisakusho
    Inventors: Kazuo Yamazaki, Kyoichi Yamamoto, Sadayuki Matsumiya, Naoki Morita
  • Patent number: 6282647
    Abstract: A programming method for flashing a read only memory (ROM) chip of a host adapter with an updated BIOS code is provided. The host adapter is connected to a host computer system. The method includes building a table having start address information and memory size information of memory space occupied in the random access memory (RAM) of the host computer system by one or more PCI host adapters which are connected to the computer system via a PCI bus. The method then moves to identifying a selected PCI host adapter having a ROM chip. A desired amount of memory space for an updated option ROM code is then mapped between the RAM of the host computer system and the ROM chip. A start address in RAM of an additional PCI host adapter that is determined to lie within the desired amount of memory space is redirected. Preferably, the redirection is temporarily made to zero.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: August 28, 2001
    Assignee: Adaptec, Inc.
    Inventors: Wendy Q. Leung, Nilesh R. Shah
  • Patent number: 6279065
    Abstract: A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: August 21, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, C. Kevin Coffee, Michael J. Collins
  • Patent number: 6260085
    Abstract: The invention relates to a changeover device which uses both analog and digital signals as input signals and supplies an analog output signal. The changeover device contains a digital-to-analog converter whose output level is adjustable. Matching to the level of the analog input signal is thus achieved. Preferred applications of the invention are picture-in-picture insertions in which an additional picture in analog form is intended to be inserted into a main picture in digital form.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: July 10, 2001
    Assignee: Infineon Technologies AG
    Inventor: Sasan Cyrusian