Abstract: Disclosed is a system and method for providing program verify adaptation for flash memory. The method includes performing an adjustment iteration, which includes accessing error counts for respective N states of a plurality of memory cells, applying a weighting to the error counts based on a binary data coding for the N states, determining a state Smin of the N states having a minimum error count Emin from the error counts, determining a state Smax of the N states having a maximum error count Emax from the error counts, determining a difference between the Emax and the Emin satisfies an error count threshold, and adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states, wherein the adjusting is a decrement when Smin is less than Smax and an increment otherwise.

Abstract: An electronic apparatus which is capable of preventing loss of data in an HDD resulting from an instantaneous power failure. The electronic apparatus is equipped with the HDD that has a nonvolatile storage area and a volatile storage area in which data is temporarily held. A control unit executes a plurality of processes including a held data writing process in which the data held in the volatile storage area is written into the nonvolatile storage area, in a predetermined order according to an off instruction by a user. In a case where a stop of the power supply to the electronic apparatus is detected, the control unit executes the plurality of processes including the held data writing process in a different order from the predetermined order.

Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

Abstract: A self-correcting secure computer system is provided. The computer system includes a read-only memory (ROM) device, a random access memory (RAM) device, and at least one processor in communication with the ROM device and the RAM device. The at least one processor is programmed to receive an activation signal; retrieve, from the ROM device, data to execute a first configuration including an encryption suite; execute, on the RAM device, the first configuration including the encryption suite; execute the encryption suite to generate a key; store the key at a first memory location; and delete volatile memory associated with the encryption suite.

Abstract: A method of performing a system watchdog operation of a data processing system using a system watchdog timer includes creating an initial question, starting a timer of the system watchdog timer, receiving an initial answer and an initial data code, calculating an expected data code in response to the initial question, and comparing the initial data code to the expected data code. In response to a mismatch between the initial data code and the expected data code, a bus error signal is generated. In response to a match, the initial answer is compared to the initial question, and in response to a match between the initial answer and the initial question, the timer is reset and the initial data code is stored as a subsequent question, but in response to a mismatch, a remedial action of the data processing system is performed.

Abstract: Weak erase detection and mitigation techniques are provided that detect permanent failures in solid-state storage devices. One exemplary method comprises obtaining an erase fail bits metric for a solid-state storage device; and detecting a permanent failure in at least a portion of the solid-state storage device causing weak erase failure mode by comparing the erase fail bit metric to a predefined fail bits threshold. In at least one embodiment, the method also comprises mitigating for the permanent failure causing the weak erase failure mode for one or more cells of the solid-state storage device. The mitigating for the permanent failure comprises, for example, changing a status of the one or more cells to a defective state and/or a retired state. The detection of the permanent failure causing the weak erase failure mode comprises, for example, detecting the weak erase failure mode without an erase failure.

Abstract: A system, method, and computer-readable medium are disclosed for performing a customer operating system installation operation. The customer operating system installation operation includes performing a customer operating system installation operation onto an information handling system, comprising: performing a customer operating system installation operation; and, performing a UEFI boot entry operation, the UEFI boot entry operation accessing a UEFI boot entry when performing the customer operating system installation operation, the UEFI boot entry operation providing a communication abstraction between a manufacturing operating system and the customer operating system.

Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

Abstract: Systems and methods for determining a source of anomaly in a cyber-physical system (CPS). A forecasting tool can obtain a plurality of CPS feature values during an input window and forecast the plurality of CPS feature values for a forecast window. An anomaly identification tool can determine a total forecast error for the plurality of CPS features in the forecast window, identify an anomaly in the cyber-physical system when the total forecast error exceeds a total error threshold, and identify at least one CPS feature as the source of the anomaly.

Abstract: In one embodiment, a device predicts a failure of a first tunnel in a software-defined wide area network (SD-WAN). The device determines that no backup tunnel for the first tunnel exists in the SD-WAN that can satisfy one or more service level agreements (SLAs) of traffic on the first tunnel, were the traffic rerouted from the first tunnel onto that tunnel. The device predicts, using a machine learning model, that a backup tunnel for the first tunnel exists in the SD-WAN that can satisfy an SLA of a subset of the traffic on the first tunnel, in response to determining that no backup tunnel exists in the SD-WAN that can satisfy the one or more SLAs of the traffic on the first tunnel. The device proactively reroutes the subset of the traffic on the first tunnel onto the backup tunnel, in advance of the predicted failure of the first tunnel.

Abstract: In an intelligent integration error handling in enterprise systems, an integration error is logged by a sender system or a receiver system in an error monitoring application. The integration error occurred in a transaction between the integrated sender system and the receiver system. Parsing the log in real-time by a worker cloak agent, a mode of integration error correction is determined based on inputs from an intelligent correction rule service. Upon determining that the mode of integration error correction is autonomous, the integration error is automatically fixed in real-time without manual intervention by the worker cloak agent. Upon determining that the mode of integration error correction is semi-autonomous, inputs from a business user is received along with a consent to fix the integration error in real-time. Correction rules are dynamically updated in a dynamic decision table. While performing correction the sender system and receiver systems are notified.

Abstract: The present disclosure provides a method for providing a fatal error of a system-on-chip product and a method for identifying a fatal error of a system-on-chip product. The system-on-chip product includes a processor. The method for providing a fatal error of a system-on-chip product includes: when a fatal error occurs, setting a port value of a preset port of the processor as a preset value corresponding to the fatal error; converting the preset value into register data accessible to an external server, such that the external server can identify the fatal error that occurs in the system-on-chip product according to the preset value when acquiring the register data. Through the present disclosure, even if the system-on-chip product does not support a baseboard management controller, the user of the baseboard can still obtain the reason for the error of the product through an out-of-band method.

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

Abstract: A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

Abstract: The present disclosure relates to a system for real-time debugging of microcontroller, the system includes a microcontroller configured in an embedded device to execute a set of instructions, the microcontroller includes a counter unit that generates a set of values for the executed set of instructions. An on-chip debugger (OCD) fetches a selective set of data packets of the set of instructions from the microcontroller. An encoder encodes the selective set of data packets to store the encoded set of data packets in a storage unit, wherein encoding of the set of data packets is performed to compress the data for minimal information size such that the external debugger unit (EDU) receives the encoded set of data packets with minimal information size through the external interface.

Abstract: A system for secure processing of intra-processor data comprising firmware configured to operate on a processor. An operating system configured to operate on the processor. Payload configured to operate on the processor. An embedded controller coupled to the firmware, the operating system and the payload, wherein the embedded controller is configured to enable messaging between the firmware, the operating system and the payload.

Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: receive, via a network, multiple discovery messages respectively from multiple information handling systems (IHSs); receive, via the network, a first message associated with a first event from a first information handling system of the multiple IHSs; determine, based at least on the first message, that none of multiple rules is associated with the first event; in response to determining that none of the multiple rules is associated with the first event, provide a second message associated with the first event to a back end information handling system (IHS); receive, from the back end IHS, data indicating how to handle the first event; add, to the multiple rules, a rule based at least on the data indicating how to handle the first event; and provide the rule to the multiple IHSs.

Abstract: Techniques for providing lifecycle handling of faults associated with a storage appliance. The techniques can include recording information or details of one or more detected faults associated with a storage appliance in a fault database, analyzing the recorded fault information/details by an analytic tool, and determining whether to perform immediate recovery or defer recovery of the detected fault(s) based at least on a recommendation of the analytic tool. In this way, taking the storage appliance offline upon occurrence of a single fault can, for the most part, be avoided. In addition, because the detection of faults is not performed within a fault domain for a filesystem handling files for a single or limited number of volume families, a deduplication domain for the files of the filesystem is not restricted to the single or limited number of volume families.

Abstract: Provided are a diagnostic model generating apparatus and a diagnostic model generating method therefor. The diagnostic model generating method may comprising: extracting at least one keyword from consultation data between a user and a consultant for resolving electronic device errors; on the basis of the at least one extracted keyword, determining a diagnostic sequence between the plurality of diagnostic commands for resolving errors and a plurality of diagnostic commands; and storing a diagnostic model comprising the plurality of determined diagnostic commands and determined diagnostic sequence.