Patents Examined by Kaushikkumar Patel
  • Patent number: 9703709
    Abstract: A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 11, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Robert Graham Isherwood, Yin Nam Ko
  • Patent number: 9697138
    Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 9697063
    Abstract: A data storage service receives a request to store data into a data storage system that consists of many physical data storage locations, each location having various physical characteristics. The data storage service determines a proper location for the data based on data placement rules applied to the physical data storage locations such that a set of proper locations is identified. The data storage service can place the data according to data placement rules.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: July 4, 2017
    Assignee: Amazon Technologies, Inc.
    Inventor: Colin Laird Lazier
  • Patent number: 9697129
    Abstract: A method, a computer program product, and a computer system for implementing multiple window based segment prefetch used for data pages that are out of sequence. A computer initiates a buffer for the segment prefetch. The computer builds up windows in the buffer, each of the windows comprising data pages among which neighboring data pages are within a predetermined distance therebetween. The computer determines whether a respective one of the windows exceeds a predetermined window size. The computer triggers the segment prefetch, in response to determining that the respective one of the windows exceeds the predetermined window size. The computer uses an asynchronous I/O to get the data pages in the respective one of the windows.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Xin Ying Yang, Xiang Zhou
  • Patent number: 9678897
    Abstract: A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 13, 2017
    Assignee: NVIDIA Corporation
    Inventors: Nicholas Wang, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Matthew Brockmeyer, Stewart Glenn Carlton
  • Patent number: 9665292
    Abstract: An information handling system includes a plurality of physical disks, a memory to store metadata for the physical disks, and a controller. The controller is configured to communicate with the physical disks and with the memory. The controller to receive a request to enable a redundant array of independent disks (RAID) mode on the physical disks, to allocate a portion of the memory to store the metadata while in the RAID mode, to store the metadata for the physical disks in each of the physical disks and in the portion of the memory, and to update and synchronize the metadata in response to a configuration change of the physical disks.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 30, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: Ashokan Vellimalai, Deepu S. Sreedhar M, Sandeep Agarwal, Anup Atluri
  • Patent number: 9652171
    Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 16, 2017
    Assignee: Cavium, Inc.
    Inventors: Enrique Musoll, Weihuang Wang
  • Patent number: 9652393
    Abstract: Provided is a method for managing a shared memory in a database server. The database server includes a shared memory manager which divides a shared memory into a plurality of memory chunks to manage the memory chunks and allocates at least one memory chunk to a cache memory manager based on a request of the cache memory manager; a cache memory manager which requests at least one of the plurality of memory chunks to the shared memory manager, wherein the database server includes a plurality of cache memory managers and the database server uses the memory chunk which is allocated to the cache memory manager as a cache memory having a predetermined purpose, and the predetermined purposes of the plurality of cache memory managers are different from each other; and a main processor which performs a database operation using the cache memory.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 16, 2017
    Assignee: TMAXDATA CO., LTD.
    Inventors: Ingyu Kang, Dongyun Yang
  • Patent number: 9639287
    Abstract: In operating a Data Storage Device (DSD) in communication with a host, a reported write command log is maintained that includes entries identifying pending write commands reported as completed to the host but whose data is not yet stored in at least one Non-Volatile Memory (NVM) of the DSD. The reported write command log is maintained to persist over power cycles. A write command is received from the host to store data in the at least one NVM and the data for the write command is buffered in a volatile memory of the DSD for storage in the at least one NVM. The reported write command log is updated to account for the write command as a pending write command reported as completed, and an indication is sent to the host reporting completion of the write command before completing storage of the data in the at least one NVM.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 2, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Albert H. Chen
  • Patent number: 9632938
    Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: April 25, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingyang Chen, Mingyu Chen, Zehan Cui, Licheng Chen
  • Patent number: 9619167
    Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Knut S. Grimsrud, Richard L. Coulson
  • Patent number: 9612976
    Abstract: In a method for managing memory pages, responsive to determining that a server is experiencing memory pressure, one or more processors identifying a first memory page in a listing of memory pages in the server. The method further includes determining whether the first memory page corresponds to a logical partition (LPAR) of the server that is scheduled to undergo an operation to migrate data stored on memory pages of the LPAR to another server. The method further includes, responsive to determining that the first memory page does correspond to a LPAR of the server that is scheduled to undergo an operation to migrate data, determining whether to evict the first memory page based on a memory page state associated with the first memory page. The method further includes, responsive to determining to evict the first memory page, evicting data stored in the first memory page to a paging space.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Swetha N. Rao
  • Patent number: 9612754
    Abstract: A method of operating a data storage system includes writing the file system data as sequential data and non-sequential data to a storage volume, the sequential data being stored in windows each having a predetermined number of consecutive data blocks and being allocated dynamically as the sequential data is written. The method includes maintaining and using a window cache to identify existing windows for storing respective newly written sequential file system data in sequence with respective earlier-written file system data for which the existing windows were previously allocated, the window cache including a set of entries indexed by an identifier of (1) a file of the file system and (2) a window-size region of the file to which sequential data is being written, the entries including respective physical window addresses identifying respective ones of the existing windows and being obtained by lookup operations using respective values of the identifier.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 4, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Diane M. Delgado, Philippe Armangau, Ahsan Rashid
  • Patent number: 9612757
    Abstract: Crash recovery with asynchronous consistent snapshots in persistent memory stores of a processing environment. A processing environment includes a user program and infrastructure-maintained data structures. The infrastructure-maintained data structures include a log of updates made to program data structures and a snapshot of the state of the program data structures. The systems and methods include writing log entries in the log to a transient memory. The log entries correspond to store instructions and memory management instructions operating on a nonvolatile memory (NVM), and input/output (I/O) operations executed by program instructions of the user program. Each of the log entries represents an effect of a corresponding operation in the program instructions. The systems and methods also include creating a snapshot in the NVM after a consistent program point based on the log of updates. The snapshot provides a rollback position during restart following a crash.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 4, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Dhruva Chakrabarti
  • Patent number: 9612950
    Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Cavium, Inc.
    Inventors: Enrique Musoll, Weihuang Wang
  • Patent number: 9606912
    Abstract: A recycling method for a solid state drive is disclosed. The method includes selecting a logical block for recycle wherein the logical block includes a plurality of pages across a plurality of flash dies. The method also includes retrieving an address map index record associated with the logical block selected for recycle. For each particular address map index stored in the address map index record, the recycling method retrieves a set of address map entries referenced by the particular address map index, determines whether any page in the logical block is referenced by the set of address map entries, and if at least one page in the logical block is referenced by the set of address map entries, the method writes the at least one page to a different logical block. The method further includes erasing the plurality of pages in the logical block.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 28, 2017
    Assignee: Seagate Technology LLC
    Inventors: Peng Xu, Alex Ga Hing Tang, LiZhao Ma, Nanshan Shu
  • Patent number: 9606942
    Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: March 28, 2017
    Assignee: Cavium, Inc.
    Inventors: Enrique Musoll, Tsahi Daniel
  • Patent number: 9594520
    Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 14, 2017
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 9594680
    Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 9594513
    Abstract: A data storage system includes an internal file system writing file system data to an underlying storage volume. File system data is written as sequential data and non-sequential data, the sequential data stored in dynamically allocated windows having a predetermined number of data blocks. Operation includes stream detection that detects and identifies sequential data by (1) applying nearness detection to identify newly written data blocks as sequential data blocks located within a predetermined address range of previously data blocks, (2) for groups of written data blocks occupying respective single files, maintaining counts of the data blocks identified by the nearness detection as sequential data blocks, and (3) as additional data blocks are newly written to the groups and not identified by the nearness detection as sequential data blocks, performing overrides identifying the additional data blocks as sequential data blocks based on the counts exceeding a predetermined threshold.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 14, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Diane M. Delgado, Philippe Armangau