Patents Examined by Keith Christianson
  • Patent number: 6548382
    Abstract: A technique for forming a gettering layer in a wafer made using a controlled cleaving process. The gettering layer can be made by implanting using beam line or plasma immersion ion implantation, or made by forming a film of material such as polysilicon by way of chemical vapor deposition. A controlled cleaving process is used to form the wafer, which is a multilayered silicon on insulator substrate. The gettering layer removes and/or attracts impurities in the wafer, which can be detrimental to the functionality and reliability of an integrated circuit device made on the wafer.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: April 15, 2003
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 6518087
    Abstract: A solar battery is provided having a structure in which at least two semiconductor thin-films are disposed one over the other between a pair of electrodes, each semiconductor thin-film differing from the other in the impurity concentration thereof and/or the type of semiconductor. Formation of at least one of the semiconductor thin-films consists of coating a liquid coating composition containing a silicon compound so as to form a coating film and a step of converting the coating film into a silicon film by heat treatment and/or light treatment.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: February 11, 2003
    Assignees: Seiko Epson Corporation, JSR Corporation
    Inventors: Masahiro Furusawa, Shunichi Seki, Satoru Miyashita, Tatsuya Shimoda, Ichio Yudasaka, Yasuo Matsuki, Yasumasa Takeuchi
  • Patent number: 6514774
    Abstract: A method of forming a step edge in a surface 12 of a crystalline substrate 10, comprising the steps of forming a layer of resist 11 over the surface 12 and removing areas of the resist 11 to expose selected areas of the surface 12, thereby forming side walls 13 in the layer of the resist 11, the side walls 13 bounding the exposed areas of the surface 12. The method further comprises exposing the resist 11 and substrate 10 to an ion beam 14, thereby etching the resist 11 and the exposed areas of the surface 12, and controlling the orientation and angle of incidence of the ion beam 14 which respect to the substrate 10 and the resist side walls 13 to form a step edge with desired angle and height characteristics. An angular position of the substrate 10 about an axis 15 formed by a normal to the surface 12 is controlled in order to control the step edge formation.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: February 4, 2003
    Assignee: Commonwealth Scientific and Industrial Research Organisation
    Inventor: Cathy Foley
  • Patent number: 6514870
    Abstract: A method is provided for preparing a substrate for processing in a chamber that has a substrate receiving portion. The substrate is positioned within the chamber in a location not on the substrate receiving portion. A gaseous flow is provided to the chamber, from which a plasma is struck to heat the substrate. After the substrate has been heated, it is moved to the substrate receiving portion for processing.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Applied Materials, Inc.
    Inventor: Kent Rossman
  • Patent number: 6509204
    Abstract: A device such as a transparent solar cell or optical filter and method of its manufacture. The method includes steps of forming a first conductive layer overlying a substrate. The method also includes forming a first amorphous silicon layer overlying the first conductive layer. A step of annealing the first amorphous silicon layer is included. The annealing step may be performed using a laser. It may also be performed by maintaining the substrate at a temperature of less than 450 degrees Celsius. A second conductive layer may be formed overlying the second amorphous silicon layer.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: January 21, 2003
    Assignee: Xoptix, Inc.
    Inventor: James P. Campbell
  • Patent number: 6500702
    Abstract: The present invention discloses a method for manufacturing thin film transistor liquid crystal display including the following steps so as to form simultaneously a via hole for contacting a drain electrode and a pixel electrode mutually and the channel of thin film transistor: forming sequentially gate insulation layer, amorphous silicon layer for channel and doped semiconductor layer for ohmic contact, and metal layer for source/drain electrode on the back substrate where the gate electrode and the storage capacitor electrode have been formed; patterning the metal layer for source/drain electrode and the doped semiconductor layer for ohmic contact through a second photolithograph process so that the source electrode, the drain electrode, and the ohmic contacts thereof may be formed; forming a passivation layer on the back substrate where the source electrode and the drain electrode have been formed; patterning the passivation layer, the amorphous silicon layer for channel, and the gate insulation layer thro
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: December 31, 2002
    Assignee: Hyundai Display Technology Inc.
    Inventors: Deuk Su Lee, Jung Mok Jun
  • Patent number: 6500738
    Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: December 31, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 6489225
    Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: December 3, 2002
    Assignee: Electron Vision Corporation
    Inventors: Matthew F. Ross, Charles Hannes, William R. Livesay
  • Patent number: 6485989
    Abstract: A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense layer so as to cover the lateral edges of the patterned sense layer. Subsequently, a globally deposited tunnel layer and fixed layer are patterned so as to define the MRAM element. Preferably, the pinned layer is patterned such that the outer lateral edges of the pinned layer is displaced in a direction parallel to the substrate from the lateral edges of the patterned sensed layer thereby reducing coupling effects between the two layers. Moreover, the use of a spacer during the process further inhibits shorting between the sense layer and the pinned layer during patterning of the pinned layer.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 26, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Karen Signorini
  • Patent number: 6486058
    Abstract: The method of forming a photoresist pattern defining a contact hole. A photoresist pattern that defines an opening therethrough is provided over a semiconductor substrate surface. Then, a layer of water-soluble organic over-coating material (WASOOM) is coated over the photoresist pattern including the opening thereof. Next, the resulting structure is flowed to shrink the size of the opening. After the resist reflow, WASOOM is removed. Thus, using the methods of the present invention, a photoresist pattern capable of forming a 0.18 &mgr;m (and below) contact hole can be formed using an inexpensive conventional optical lithography system. Further, because WASOOM is water-soluble, WASOOM can be substantially completely removed from the photoresist pattern using a simple cleaning process, i.e., water rinse, after baking for resist reflow. Thus, the process steps are simplified and the problems such as the difficulty in CD control and the environmental issues are avoided.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: November 26, 2002
    Assignee: Integrated Device Technology, Inc.
    Inventor: Jun-Sung Chun
  • Patent number: 6482682
    Abstract: The invention discloses a manufacturing method for improving the reliability of polysilicon thin film transistors to solve electric leaking problem due to the roughness of polysilicon layer surface. In the thin film transistor manufacturing process, a polysilicon layer surface is oxidized to produce a silicon oxide layer which is then removed by an etching solution. This method can planarize bumps on the polysilicon layer generated due to re-crystallization so as to effectively lower the roughness of the polysilicon surface, thus increasing the reliability of thin film transistors.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: November 19, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Jeng-Hung Sun, Wen-Tung Wang
  • Patent number: 6482752
    Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: November 19, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Hiroyuki Shimada, Mitsunori Sakama, Hisashi Abe, Satoshi Teramoto
  • Patent number: 6483165
    Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: November 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Masatoshi Ishikawa
  • Patent number: 6482704
    Abstract: In a method for manufacturing a silicon carbide semiconductor device including a gate oxide film formed on a surface channel layer, the gate oxide film is formed by a thermal oxidation treatment that is performed at conditions under which a recrystallization reaction between silicon dioxide (SiO2) and carbon (C) occurs to produce silicon carbide (SiC) with a Gibbs free energy G3 being negative. The recrystallization reaction is expressed by a chemical formula of SiO2+3C→SiC+2CO+G3. Accordingly, residual carbon can be reduced at an interface between the gate oxide film and the surface channel layer.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 19, 2002
    Assignee: Denso Corporation
    Inventors: Shinji Amano, Eiichi Okuno, Tsuyoshi Yamamoto
  • Patent number: 6479311
    Abstract: The present invention provides a micromechanical or microoptomechanical structure. The structure is produced by a process comprising defining a pattern on a single crystal silicon layer separated by an insulator layer from a substrate layer; defining a structure in the single-crystal silicon layer; depositing and etching a polysilicon layer on the single crystal silicon layer, with remaining polysilcon forming mechanical or optical elements of the structure; and releasing the formed structure.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: November 12, 2002
    Assignees: Microscan Systems, Inc., Xerox Corporation
    Inventors: Bruce R. Scharf, Joel A. Kubby, Jingkuang Chen, Peter M. Gulvin, Chuang-Chia Lin, Alex T. Tran
  • Patent number: 6475840
    Abstract: An insulated gate field effect transistor comprises a silicon channel region. The silicon is crystallized by heat annealing while a suitable metal element such as nickel helps the crystallization. The crystallization proceeds in the silicon film laterally from the portion where the nickel is directly introduced. The TFT is arranged in such a manner that the source-drain direction of the TFT is aligned with the direction of the crystal growth or intersects with the crystal growth direction at a desired direction.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: November 5, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Hisashi Ohtani, Satoshi Teramoto
  • Patent number: 6472293
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 29, 2002
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventor: Tadatomo Suga
  • Patent number: 6472248
    Abstract: A photovoltaic element having a stacked structure comprising a first semiconductor layer containing no crystalline phase, a second semiconductor layer containing approximately spherical microcrystalline phases, and a third semiconductor layer containing pillar microcrystalline phases which are stacked in this order, wherein said spherical microcrystalline phases of said second semiconductor layer on the side of said third semiconductor layer have an average size which is greater than that of said spherical microcrystalline phases of said second semiconductor layer on the side of said first semiconductor layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: October 29, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsushi Shiozaki, Masafumi Sano, Toshimitsu Kariya, Takaharu Kondo, Makoto Higashikawa, Koichi Matsuda
  • Patent number: 6472300
    Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: October 29, 2002
    Assignee: Technologies and Devices International, Inc.
    Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
  • Patent number: RE38072
    Abstract: A fabrication process for a semiconductor device including a plurality of semiconductor layers, the plurality of semiconductor layers including at least a nitrogen-containing alloy semiconductor AlaGabIn1-a-bNxPyAszSb1-x-y-z (0≦a≦1, 0≦b≦1, 0<x<1, 0≦y<1, 0≦z<1), and a method of making the semiconductor device and apparatus. For at least two semiconductor layers out of the plurality of semiconductor layers, a value of lattice strain of said at least two semiconductor layers is set at less than a critical strain at which misfit dislocations are generated at an interface between said two adjacent semiconductor layers.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Kondo, Kazuhisa Uomi, Hitoshi Nakamura