Abstract: A P-I-N type photovoltaic device is manufactured by a process wherein the deposition rate of the intrinsic layer is controlled so that a portion of the intrinsic layer which is closest to the P-I interface, and which comprises at least 10% of the thickness of the intrinsic layer, is deposited at a rate which is less than the average rate at which the entire intrinsic layer is deposited.

Abstract: A semiconductor device of planar structure has a pn-junction (10) formed by a first layer (1) doped according to a first conductivity type, n or p, and on top thereof a second layer (2) doped according to a second conductivity type. The second layer has a higher doping concentration than the first layer and a lateral edge thereof is provided with an edge termination with second zones of said second conductivity type separated by first zones (4) of said first conductivity type arranged so that the total charge and/or the effective sheet charge density of dopants according to said second conductivity type is decreasing towards the laterally outer border (8) of the edge termination. A third layer (5) doped according to said first conductivity type is arranged on top of said second layer at least in the region of the edge termination for burying the edge termination of the device thereunder.

Abstract: The present invention relates to patterning methods for organic devices, and more particularly to patterning methods using a die. A first layer of organic materials is deposited over a substrate, followed by a first electrode layer. A first patterned die having a raised portion is then pressed onto the first electrode layer, such that the raised portion of the first patterned die contacts portions of the first electrode layer. The patterned die is removed, such that the portions of the first electrode layer in contact with the raised portions of the first patterned die are removed. In one embodiment of the invention, a second organic layer is then deposited over the first electrode layer, followed by a second electrode layer. A second patterned die having a raised portion is pressed onto the second electrode layer, such that the raised portion of the second patterned die contacts portions of the second electrode layer.

Abstract: A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.

Abstract: A composite light-emitting device according to the present invention includes a light-emitting element including a transparent substrate and a multilayer structure formed on the substrate. The multilayer structure includes first and second semiconductor layers of first and second conductivity types, respectively. The device further includes a submount member for mounting the light-emitting element thereon. The principal surface of the submount member faces the multilayer structure. The submount member is electrically connected to the light-emitting element. The light-emitting element is covered with a wavelength-shifting resin member. The resin member is provided on the principal surface of the submount member and contains a photofluorescent or filtering compound. The photofluorescent compound shifts the wavelength of radiation that has been emitted from the light-emitting element, while the filtering compound partially absorbs the radiation.

Abstract: In an active matrix semiconductor display device in which pixel TFTs and driver circuit TFT are formed on the same substrate in an integral manner, the cell gap is controlled by gap retaining members that are disposed between a pixel area and driver circuit areas. This makes it possible to provide a uniform cell thickness profile over the entire semiconductor display device. Further, since conventional grainy spacers are not used, stress is not imposed on the driver circuit TFTs when a TFT substrate and an opposed substrate are bonded together. This prevents the driver circuit TFTs from being damaged.

Abstract: A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

Abstract: A method of forming a contact to a substrate includes forming insulating material comprising a substantially amorphous outer surface over a substrate node location. A contact opening is etched through the insulating material over the node location. The node location comprises an outwardly exposed substantially crystalline metal silicide surface. The substrate with outwardly exposed substantially crystalline metal silicide node location surface is provided within a chemical vapor deposition reactor. A gaseous precursor including silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed substantially crystalline metal silicide node location surface and not on the insulating material.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.

Abstract: A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby

Abstract: A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

Abstract: This invention increases the overlapped area between the diffusion area and the borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in a photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases the overlapped area between the borderless contact and the active area, and reduces borderless contact leakage.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate (105). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the “on” state.

Abstract: A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide layer obtained via chemical vapor deposition procedures using tetraethylorthosilicate (TEOS), as a source, has been developed. To densify the underlying thin silicon oxide layer an anneal procedure usually performed after implantation of ions used for a lightly doped source/drain region, is delayed and performed after deposition of the thin silicon oxide layer. The anneal procedure is then used for both activation of the lightly doped source/drain ions, and densification of the thin silicon oxide layer. The etch rate of the densified silicon oxide layer, in dilute hydrofluoric acid procedures is now reduced allowing the underlying silicon oxide component, of the composite insulator spacer, to survive subsequent wet clean procedures employing dilute hydrofluoric acid.

Abstract: A capacitor comprising a first electrode, a second electrode, and a dielectric material and an organic isolation matrix forming at least one layer between the first and second electrodes is provided. Also provided are other integrated circuit devices containing a dielectric material and an organic isolation matrix in contact with the dielectric material.