Patents Examined by Kenneth Lo
  • Patent number: 8281073
    Abstract: Disclosed is an information processing apparatus equipped with first and second CPUs, as well as a method of controlling this apparatus. When the first CPU launches an operating system for managing a virtual memory area that includes a first cache area for a device, the first CPU generates specification data, which indicates the corresponding relationship between the first cache and a second cache for the device and provided in a main memory, and transfers the specification data to the second CPU. In accordance with the specification data, the second CPU transfers data, which has been stored in the device, to a physical memory corresponding to a cache to which the first CPU refers. As a result, the first CPU accesses the first cache area is thereby capable of accessing the device at high speed.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 2, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Hara
  • Patent number: 8281083
    Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Eliezer Weissmann, Itamar Kazachinsky, Iris Sorani, Yair Kazarinov
  • Patent number: 8261033
    Abstract: A method and system for migrating massive amounts of data in a secure and traceable fashion using a distributed storage system is described. Data shuttle storage devices moves large quantities of content from one source location to one or more target locations by first acting in local communication with the source location, then being physically moved to a location where a shuttle storage device may be in local communication with the target location. This migration does not compromise data accessibility, reliability, or security. Dynamic configurable policy-driven data placement specifies the number and location of multiple copies of each digital data object. Each digital data object replica remains traceable even as the hardware onto which it is stored is being relocated. The content remains accessible at any time.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: September 4, 2012
    Assignee: Bycast Inc.
    Inventors: David Slik, Jay Austin, Angela Cheng, Alvin Lam, Markus Lampert, Michael Montour
  • Patent number: 8244977
    Abstract: Methods, systems, and products are provided that display memory statistics for a keydrive that do not require the keydrive to be plugged into another device. Displaying memory statistics according to embodiments of the present invention include receiving a command resulting in a change to the memory usage of the keydrive, calculating memory statistics describing the current state of memory usage of the keydrive, storing the memory statistics in memory on the keydrive, and displaying the memory statistics on a display on the keydrive. Calculating memory statistics describing the current state of memory usage of the keydrive may be carried out by calculating a total memory usage of the keydrive. Calculating memory statistics describing the current state of memory usage of the keydrive may also be carried out by calculating a percent of total memory used.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Phani Gopal V. Achanta, Riaz Y. Hussain, Scott Thomas Jones
  • Patent number: 8245008
    Abstract: A system and method for allocating memory to multi-threaded programs on a Non-Uniform Memory Access (NUMA) computer system using a NUMA-aware memory heap manager is disclosed. In embodiments, a NUMA-aware memory heap manager may attempt to maximize the locality of memory allocations in a NUMA system by allocating memory blocks that are near, or on the same node, as the thread that requested the memory allocation. A heap manager may keep track of each memory block's location and satisfy allocation requests by determining an allocation node dependent, at least in part, on its locality to that of the requesting thread. When possible, a heap manger may attempt to allocate memory on the same node as the requesting thread. The heap manager may be non-application-specific, may employ multiple levels of free block caching, and/or may employ various listings that associate given memory blocks with each NUMA node.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: August 14, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patryk Kaminski, Keith Lowery
  • Patent number: 8219759
    Abstract: Apparatus, systems, and methods may operate to send a window copy message including changed window identification information to a remote node when metadata associated with a changed foreground window at a local node has been cached, and otherwise, to locally cache the window metadata and send the window metadata and window pixel data to the remote node. When a preselected minimum bandwidth connection is not available between the local node and the remote node, additional operations may include sending a rectangle paint message including changed rectangle identification information to the remote node when rectangle metadata associated with a changed rectangle of a designated minimum size at the local node has been cached, and otherwise, to locally cache the rectangle metadata and send the rectangle metadata and rectangle pixel data to the remote node. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Novell, Inc.
    Inventors: Ravi kiran Gokaraju, Sudhir Reddy Nathaala
  • Patent number: 8219770
    Abstract: A storage system including: a virtualization apparatus having a control unit, said control unit setting an actual volume for storing data sent from a host apparatus, formed in a storage area provided by a physical disk; and a virtual volume paired with the actual volume, for storing replicated data for the data; and an external storage apparatus having a logical volume that functions as an actual storage area for the virtual volume; and a tape associated with the logical volume, for storing the replicated data; wherein the external storage apparatus has a copy unit for copying the replicated data stored in the logical volume to the tape.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 10, 2012
    Assignees: Hitachi, Ltd., Hitachi Computer Peripherals Co., Ltd.
    Inventor: Kazuhiro Usami
  • Patent number: 8205041
    Abstract: A virtual tape apparatus is interposed between a host and a tape device so as to store data transmitted from the host to a logical tape volume. The virtual tape apparatus includes: a data communication unit that receives data transmitted from the host; a RAID device having a logical tape volume for storing the data; a management table that manages attribute information of data stored in the physical tape volume; a position determination section that determines the write starting position of the data stored in the logical tape volume on the physical tape volume based on the management table; and a drive control unit that writes data in the logical tape volume to the physical tape volume based on a result of the determination.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 19, 2012
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Otsuka
  • Patent number: 8195911
    Abstract: A memory other than a non-volatile memory in a numerical controller is divided into a plurality of memory areas in response to a command from a computer connected to the numerical controller. Whether a machining program has been stored in each of the divided memory areas is decided before a machining program stored on a hard disk in the computer is transferred to the memory other than the non-volatile memory. The machining program stored on the hard disk is then written to an area for which it is determined that no machining program is stored.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: June 5, 2012
    Assignee: FANUC Ltd.
    Inventors: Takahiko Endo, Yasushi Takeuchi
  • Patent number: 8195901
    Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael L. Harper, Craig A. Klein, Gregg S. Lucas, Mary A. J. Marquez, Robert E. Medlin
  • Patent number: 8190809
    Abstract: A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), ?Q+mod(2A,Q), ±1 or ±prime to , where ?<S<+.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: May 29, 2012
    Assignee: Efficient Memory Technology
    Inventor: Maurice L. Hutson
  • Patent number: 8185704
    Abstract: A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 8171217
    Abstract: A storage apparatus comprises a disk device and a disk adapter for controlling the disk device. The disk adapter controls the disk device and forms a data volume and a pool volume, creates a data block for parity data, compresses write data and the created parity data, and stores a number of compressed data blocks equal to or less than a predetermined number and stores compressed parity data that are within a predetermined size in storage areas in an actual volume, and stores the remaining compressed data blocks of a number greater than the predetermined number and compressed parity data that exceed the predetermined size in storage areas in the pool volume corresponding to a virtual volume.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: May 1, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Muto, Isamu Kurokawa, Ran Ogata, Kazue Jindo
  • Patent number: 8151079
    Abstract: Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server 1010 groups together logical volumes which use the same physical disk of a storage device 1020 as a volume group and allocates a storage area on the physical disk to be used on a priority basis by this volume group to the volume group, and thereby a physical arrangement according to a present physical arrangement of the logical volume can be performed when an automatic expansion of the logical volume is performed thereafter so that the I/O performance deterioration of the computer caused by a mutual interference is avoided at the time of access from the computer 1030 to the storage device 1020.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 3, 2012
    Assignee: Hitatchi, Ltd.
    Inventors: Jun Mizuno, Takeshi Ishizaki
  • Patent number: 8127098
    Abstract: In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing in a processor; determining that the write attempts to establish a first mode in the processor in which privilege level protection is disabled and paging is disabled; and causing the guest to execute in a second mode in which privilege level protection is disabled and paging is enabled instead of the first mode. A computer accessible medium comprising instruction implementing at least a portion of the method is also described.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 28, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alexander C. Klaiber, Kevin J. McGrath, Hongwen Gao
  • Patent number: 8117376
    Abstract: Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of memory modules having one or more nonvolatile memory chips, and a controller for controlling the reading and writing of data from and in each memory module. The memory module decides the nonvolatile memory chip to become a copy destination of data stored in the nonvolatile memory when a failure occurs in the nonvolatile memory chip of a self memory module, and copies the data stored in the failed nonvolatile memory chip to the nonvolatile memory chip decided as the copy destination.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: February 14, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Masateru Hemmi
  • Patent number: 8069305
    Abstract: A disk is divided into K angular regions. A log write request is replicated K times and K number of identical log writes are issued to the disk to be written to each of the angular regions of the log. Upon completion of the first write, the application requesting the log write is informed of its completion resulting in a reduction of rotational latency by a factor of K.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: November 29, 2011
    Assignee: Oracle America, Inc.
    Inventors: Olaf Manczak, Eric J. Kustarz
  • Patent number: 8055857
    Abstract: A memory device has a first memory area and a second memory area. A method for operating the memory device includes a write access to the first memory area and a read access to the second memory area.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: November 8, 2011
    Assignee: Qimonda AG
    Inventors: Martin Brox, Rex Kho
  • Patent number: 8051270
    Abstract: A memory controller for reducing a time to create an address management table during initialization of a memory card. The memory controller includes a read-write memory for temporarily storing the address management table and a second memory controller for writing, in a nonvolatile memory, an address management table temporarily stored in the read-write memory. The second memory controller also writes address range specifying information that specifies an address range, when a data writing destination is changed from a first address range to a second address range. The memory controller includes an address management table generator for reading distributed management information used for managing a state of at least one physical block included in the destination address range specified by the address range specifying information during initialization, and to generate the address management table based on the distributed management information.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: November 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Daisuke Kunimune, Masahiro Nakanishi, Manabu Inoue, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno
  • Patent number: 8037276
    Abstract: Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server 1010 groups together logical volumes which use the same physical disk of a storage device 1020 as a volume group and allocates a storage area on the physical disk to be used on a priority basis by this volume group to the volume group, and thereby a physical arrangement according to a present physical arrangement of the logical volume can be performed when an automatic expansion of the logical volume is performed thereafter so that the I/O performance deterioration of the computer caused by a mutual interference is avoided at the time of access from the computer 1030 to the storage device 1020.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: October 11, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Jun Mizuno, Takeshi Ishizaki