Patents Examined by Kenneth Parker
  • Patent number: 11031294
    Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
  • Patent number: 11031436
    Abstract: A display device includes a substrate, a pixel area, and a plurality of data lines. The substrate includes display and non-display areas. The pixel area is in the display area and includes a first pixel column and a second pixel column. The pixels in the first and second columns emit light of different colors. The data lines are respectively coupled to the first pixel column and the second pixel column. In the non-display area, a data line is coupled to one of the first or second pixel columns corresponding to a color on which influence of a resistance is greater than on another color. The data lines has a line or contact structure with a resistance less than a resistance of a line or contact structure of a remaining data line coupled to a remaining pixel column.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 8, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Ja Kwon, Won Kyu Kwak, Hwan Soo Jang, Seung Yeon Cho, Hyun Ae Park
  • Patent number: 11018085
    Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Naoya Inoue, Dong Won Kim, Young Woo Cho, Ji Won Kang, Song Yi Han
  • Patent number: 11004756
    Abstract: A semiconductor device includes: a base plate; a semiconductor chip mounted on the base plate; a case surrounding the semiconductor chip on the base plate; an electrode terminal connected to the semiconductor chip; a sealing material covering an upper face of the base plate, the semiconductor chip and a part of the electrode terminal in the case; and a lid fastened to the case above the sealing material, wherein the electrode terminal is not exposed on an upper face of the sealing material, and there is a gap between the upper face of the sealing material and a lower face of the lid.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: May 11, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kota Ohara, Manabu Matsumoto, Yoshitaka Otsubo
  • Patent number: 10991730
    Abstract: An active matrix substrate includes, in a peripheral region that is disposed around a display region, a connecting portion formation region in which a plurality of line connecting portions are arranged. Each line connecting portion includes: a lower connecting portion; an organic insulating layer disposed on the lower connecting portion so as to be in contact with the lower connecting portion, the organic insulating layer having at least one aperture through which a part of the lower connecting portion is exposed; and an upper connecting portion disposed on the organic insulating layer and in the at least one aperture, the upper connecting portion being directly in contact with the part of the lower connecting portion within the at least one aperture. The organic insulating layer extends into an adjoining region that adjoins the connecting portion formation region.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yoshio Dejima
  • Patent number: 10991855
    Abstract: A white light emitting device includes a blue LED chip having a dominant emission wavelength of about 440-465 nm, and a phosphor layer configured to be excited by the dominant emission wavelength of the blue LED chip. The phosphor layer includes a first phosphor having a peak emission wavelength of about 480-519 nm, a second phosphor having a peak emission wavelength of about 520-560 nm, and a third phosphor having a peak emission wavelength of about 620-670 nm. The first phosphor and the second phosphor both have a garnet structure as represented by A3B5O12:Ce, A is selected from the group consisting of Y, Lu, and a combination of thereof, and B is selected from the group consisting of Al, Ga, and a combination of thereof.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 27, 2021
    Assignee: Lextar Electronics Corporation
    Inventors: Cheng-Ping Chang, Zong-Han Yu, Kuo-Chan Hung
  • Patent number: 10985245
    Abstract: The disclosure relates to a semiconductor device including a first planar field effect transistor cell and a second planar field effect transistor cell. The first planar field effect transistor cell and the second planar field effect transistor cell are electrically connected in parallel and each include a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. A gate electrode of the first field effect transistor cell is electrically connected to a source terminal, and a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Christian Kampen
  • Patent number: 10985080
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Patent number: 10985062
    Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10964707
    Abstract: A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second region being a peripheral circuit region, first gate structures in a first direction on the first region and being spaced apart from each other in a second direction, second gate structures in the first direction on the second region and being spaced apart from each other in the second direction, the first and second gate structures being aligned with each other, a first insulating structure in the second direction on the buffer region between the first and the second regions along an entire length of each of the first and second regions in the second direction, and a second insulating structure on the first region and in contact with a part of the plurality of first gate structures.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seol Un Yang, Lak Gyo Jeong, Hee Bum Hong
  • Patent number: 10964687
    Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prahbu
  • Patent number: 10957754
    Abstract: A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: June Woo Lee, Shin Moon Kang, Byoung Ki Kim, Hee Kyung Kim, Hyun Chui Son, Yun-Mo Chung, Jae Beom Choi
  • Patent number: 10957816
    Abstract: An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Jack O. Chu, Christos Dimitrakopoulos, Jeehwan Kim, Hongsik Park, Devendra K. Sadana
  • Patent number: 10957635
    Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nazila Dadvand, Sreenivasan Koduri, Benjamin Stassen Cook
  • Patent number: 10950554
    Abstract: Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 10950718
    Abstract: A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Anton Mauder, Thomas Kuenzig, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 10937718
    Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hua Chen, Hao-Yi Tsai, Yu-Feng Chen
  • Patent number: 10930666
    Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10930667
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 10926288
    Abstract: A coating sequence includes supplying a resist liquid onto a wafer under a condition that a liquid puddle of the resist liquid is formed at a central portion thereof; supplying, while rotating the wafer at a first rotation speed where the liquid puddle stays at an inner side than an edge of the wafer, a diluting liquid and moving a supply position of the diluting liquid from an outside of the liquid puddle to an edge portion thereof; moving, after the moving of the supply position from the outside to the edge portion, the supply position from the edge portion to the outside while continuously rotating the wafer at the first rotation speed; and rotating, after the moving of the supply position from the edge portion to the outside, the wafer at a rotation speed higher than the first rotation speed to diffuse the resist liquid toward the edge.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 23, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Teppei Takahashi