Patents Examined by Kenneth Parker
  • Patent number: 11410923
    Abstract: A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen
  • Patent number: 11374166
    Abstract: A spin current magnetization rotational element according to the present disclosure includes a first ferromagnetic metal layer configured for a direction of magnetization to be changed and a spin-orbit torque wiring extending in a direction intersecting a lamination direction of the first ferromagnetic metal layer and bonded to the first ferromagnetic metal layer. The spin-orbit torque wiring includes a narrow portion, and at least a part of the narrow portion constitutes a junction to the first ferromagnetic metal layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: June 28, 2022
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11355607
    Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Larsen, David A. Daycock, Kunal Shrotri
  • Patent number: 11355705
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 7, 2022
    Assignee: Kioxia Corporation
    Inventor: Kotaro Noda
  • Patent number: 11355656
    Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the base, and the photosensitive element is configured to receive a light beam traveling along an optical axis.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 7, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chen-Er Hsu, Sin-Jhong Song, Chi-Fu Wu, Hao-Yu Wu, Tsutomu Fukai, Ming-Hung Wu
  • Patent number: 11348828
    Abstract: An interconnect structure includes a damascene structure, an inter-metal dielectric (IMD), a dielectric block and a metal via. The inter-metal dielectric layer is over the damascene structure. The dielectric block is embedded in the IMD layer and has a different etch selectivity than the IMD layer. The metal via is in the IMD layer and through the dielectric block to electrically connect the damascene structure.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jye-Yen Cheng, Chen-Yu Shyu, Ming-Shuoh Liang
  • Patent number: 11342267
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Po-Hao Chang, Yi-Jou Lin, Hung-Chuan Chen
  • Patent number: 11342440
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 24, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ishan Wathuthanthri, Ken Alfred Nagamatsu, William J. Sweet, James T. Kelliher, John S. Mason, Jr., Jonah Paul Sengupta
  • Patent number: 11335749
    Abstract: An organic light-emitting display apparatus includes a plurality of pixels. At least one of the pixels includes a first conductive layer over a substrate, a first organic insulating layer including a first opening exposing a portion of the first conductive layer, a first inorganic insulating layer over the first organic insulating layer and including a second opening exposing the portion of the first conductive layer exposed through the first opening, and a second conductive layer on the first inorganic insulating layer and contacting the portion of the first conductive layer exposed through the first opening and the second opening.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kihoon Kim, Deukjong Kim, Keunsoo Lee, Donghyun Lee
  • Patent number: 11315831
    Abstract: A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, James J. Kelly
  • Patent number: 11315999
    Abstract: The disclosure provides an array substrate, a display panel, a display device, and a method for fabricating the same. The array substrate provided by the present disclosure includes a substrate, a wiring on the substrate, an insulating layer covering the wiring, and a protrusion on the insulating layer and located in a non-display region of the array substrate. Wherein the protrusion is adjacent to the wiring, and wherein a surface, away from the base substrate, of the protrusion is further away from the base substrate than a surface, away from the base substrate, of a portion of the first insulating layer covering the wiring.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 26, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu Ai, Xuewu Xie, Jian Wu
  • Patent number: 11302775
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 12, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 11302688
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 11289477
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Blandine Duriez, Georgios Vellianitis
  • Patent number: 11289553
    Abstract: A display device includes a substrate including a display region and a peripheral region, display structures at the display region of the substrate, a plurality of blocking structures at the peripheral region of the substrate wherein the blocking structures have heights different from each other, an organic layer on the display structures and the blocking structures, and an inorganic layer on the organic layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 29, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Youl Lee, Yeon-Heok You, Sang-Won Seo, Jung-Ju Yu
  • Patent number: 11264401
    Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 1, 2022
    Inventors: Jun Hyoung Kim, Kwang Soo Kim, Seok Cheon Baek, Geun Won Lim
  • Patent number: 11264264
    Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 1, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi Noma, Noboru Okubo, Yusheng Lin
  • Patent number: 11257987
    Abstract: A structure with micro light-emitting device includes a substrate, at least one micro light-emitting device, a holding structure, and at least one buffer structure. The micro light-emitting device is disposed on the substrate, and there is a vertical distance between the micro light-emitting device and the substrate. The holding structure is disposed on the substrate and directly contacts the micro light-emitting device. The buffer structure directly contacts the holding structure. Here, a Young's modulus of the buffer structure is smaller than a Young's modulus of the holding structure.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: February 22, 2022
    Assignee: PlayNitride Inc.
    Inventors: Yu-Yun Lo, Chih-Ling Wu, Yi-Min Su
  • Patent number: 11239261
    Abstract: A display device having a gate driver which may reduce generation of ripple at the output of the gate drive includes: a substrate; and a driver circuit including a thin film transistor disposed on the substrate, the thin film transistor including: a first gate electrode disposed on the substrate; a semiconductor layer disposed on the first gate electrode to overlap a part of the first gate electrode, the semiconductor layer including channel, source, and drain regions; a second gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer and respectively connected to the source region and the drain region, wherein a first area formed by the overlapping portion of the first gate electrode and the drain region has a different size than a second area formed by the overlapping portion of the first gate electrode and the source region.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 1, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheol-Gon Lee, Il-Joo Kim, Mee Hye Jung, Jun Ki Jeong
  • Patent number: 11239292
    Abstract: Provided are an array substrate, a display panel, a display apparatus and a preparation method therefor. The array substrate comprises: a base substrate; and multiple pixel units arranged on one side of the base substrate, each of the pixel units comprising: a thin-film transistor and an electroluminescent structure, and a shading structure located between the thin-film transistor and the base substrate, wherein the thin-film transistor comprises: an active layer located on one side, away from the base substrate, of the shading structure; the electroluminescent structure comprises: first electrodes for driving the pixel units; and one of the shading structure and the active layer is a same-layer structure fabricated by the same mask plate as the first electrodes so as to reduce the number of mask procedures required in preparation of an array substrate.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 1, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Jiangbo Chen, Youngsuk Song, Wenjun Hou, Lei Zhao, Guoying Wang