Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.

Abstract: Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

Abstract: A method of manufacturing a light emitting element includes forming an n-side electrode at a lateral surface of an n-type semiconductor layer so as not to cover a light extraction surface. Using a portion of a silicon substrate left on an n-type semiconductor layer as a mask, an insulating film formed at a lateral surface of a semiconductor layered body is removed, to expose a lateral surface of the n-type semiconductor layer and a lateral surface of a resin layer. An n-side electrode positioned between the lateral surface of the n-type semiconductor layer and the lateral surface of the resin layer and connected to the exposed lateral surface of the n-type semiconductor layer is formed. Thereafter, the portion of the silicon substrate is removed, to expose the n-type semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a source region and a drain region in a semiconductor substrate, and a bit line over the source region. The semiconductor device also includes a first epitaxial structure over the drain region, and a capacitor contact over the first epitaxial structure. A bottom surface of the capacitor contact is higher than a bottom surface of the bit line.

Abstract: The present disclosure relates to a method for preparing a semiconductor device. The method includes forming a source region and a drain region in a semiconductor substrate, and forming a bit line over the source region. The method also includes growing a first epitaxial structure over the drain region. A top surface of the first epitaxial structure is higher than a bottom surface of the bit line. The method further includes forming a capacitor contact over the first epitaxial structure.

Abstract: Radiation detecting-structures and fabrications methods thereof are presented. The methods include, for instance: providing a substrate, the substrate including at least one trench extending into the substrate from an upper surface thereof; and epitaxially forming a radiation-responsive semiconductor material layer from one or more sidewalls of the at least one trench of the substrate, the radiation-responsive semiconductor material layer responding to incident radiation by generating charge carriers therein. In one embodiment, the sidewalls of the at least one trench of the substrate include a (111) surface of the substrate, which facilitates epitaxially forming the radiation-responsive semiconductor material layer. In another embodiment, the radiation-responsive semiconductor material layer includes hexagonal boron nitride, and the epitaxially forming includes providing the hexagonal boron nitride with an a-axis aligned parallel to the sidewalls of the trench.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

Abstract: An organic light-emitting display apparatus includes: a substrate; first and second pixel electrodes on the substrate and spaced from each other; an insulating layer between the first and second pixel electrodes, the insulating layer covering ends of the first and second pixel electrodes, and having a step height difference; an auxiliary electrode on the insulating layer; first and second intermediate layers on the first and second pixel electrodes, the first and second intermediate layers being spaced from each other, and including first and second light-emitting layers, respectively; first and second opposite electrodes on the first and second intermediate layers, the first and second opposite electrodes being spaced from each other, and in contact with the auxiliary electrode; and first and second passivation layers on the first and second opposite electrodes, the first and second passivation layers being spaced from each other, and covering the first and second opposite electrodes, respectively.

Abstract: A micro-LED mounting structure includes a first layer having a conductive pad disposed on a surface thereof, a second layer including a first surface, a second surface opposite the first surface and disposed on the surface of the first layer, and a via-hole extending from the conductive pad of the first layer to the first surface and including a conductive material, and a micro-LED disposed on the first surface of the second layer to be electrically connected with the conductive material included in the via-hole. The via-hole includes a first opening in the first surface of the second layer and in which the conductive material is formed, the conductive material of the first surface provides a conductive area on a portion of the first surface of the second layer, and the conductive area and an area within a specified area of the conductive area define a substantially flat surface.

Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

Abstract: A semiconductor device, an integrated fan-out package and a method of forming the same are disclosed. In some embodiments, a semiconductor device includes a substrate, a conductive layer, a passivation layer and a bump structure. The substrate has at least one electronic component therein. The conductive layer has a plurality of lines patterns over and electrically connected to the at least one electronic component. The passivation layer is over the conductive layer. The bump structure has a plurality of protruding parts penetrating through the passivation layer and electrically connected to the lines patterns of the conductive layer.

Abstract: A spin current magnetization rotational element according to the present disclosure includes a first ferromagnetic metal layer configured for a direction of magnetization to be changed and a spin-orbit torque wiring extending in a direction intersecting a lamination direction of the first ferromagnetic metal layer and bonded to the first ferromagnetic metal layer. The spin-orbit torque wiring includes a narrow portion, and at least a part of the narrow portion constitutes a junction to the first ferromagnetic metal layer.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

Abstract: A photosensitive module is provided. The photosensitive module includes a base, an integrated package substrate, and a photosensitive element. The integrated package substrate is connected to the base. The integrated package substrate has a plurality of first electronic components, and the first electronic components are housed inside the integrated package substrate without being exposed to external environment. The photosensitive element is connected to the base, and the photosensitive element is configured to receive a light beam traveling along an optical axis.

Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.