Patents Examined by Kenneth Parker
  • Patent number: 10388841
    Abstract: A light emitting device may include a substrate; a body which is disposed on the substrate and has a first hole having a predetermined size and a light emitting chip which is disposed within a cavity formed by the substrate and the first hole of the body. A cap may be disposed on the body and may have a second hole having a predetermined size. A transparent window may be disposed in the second hole. A lower portion of the cap is divided into a first surface and a second surface more projecting downwardly than the first surface, and at least a portion of the first surface is attached and fixed to the body.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 20, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Byung Mok Kim, Hiroshi Kodaira, Su Jung Jung, Bo Hee Kang, Young Jin No, Yuichiro Tanda, Satoshi Ozeki
  • Patent number: 10378913
    Abstract: A navigation apparatus includes: a current-position information acquisition section obtaining measured current-position information; a camera section obtaining a captured image of a subject; a direction detection section detecting a direction when obtaining the captured image by the camera section; from characteristic-point information related to multiple predetermined characteristic points stored in a storage section, a characteristic-point information extraction section extracting the characteristic-point information related to the characteristic points located in the vicinity of the current position and in a range shown in the direction; and a control section displaying the captured image on a display section, wherein the control section displays a predetermined direction line indicating a distance from the current position on the captured image, obtains a distance and a direction from the current position to the characteristic point, and displays the characteristic-point information at a position correspo
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 13, 2019
    Assignee: Sony Corporation
    Inventor: Hiromasa Miyata
  • Patent number: 10375287
    Abstract: Systems and methods for analyzing scenes from cameras imaging an event, such as a sporting event broadcast, are provided. Systems and methods include detecting and tracking patterns and trails. This may be performed with intra-frame processing and without knowledge of camera parameters. A system for analyzing a scene may include an object characterizer, a foreground detector, an object tracker, a trail updater, and a video annotator. Systems and methods may provide information regarding centers and spans of activity based on object locations and trails, which may be used to control camera field of views such as a camera pose and zoom level. A magnification may be determined for images in a video sequence based on the size of an object in the images. Measurements may be determined from object trails in a video sequence based on an effective magnification of images in the video sequence.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 6, 2019
    Assignee: Disney Enterprises, Inc.
    Inventors: Smadar Gefen, Gregory House, Yuecheng Zhang
  • Patent number: 10373945
    Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 6, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zheng Bian
  • Patent number: 10367055
    Abstract: The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: July 30, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10345382
    Abstract: A method and a related terminal for displaying battery power to improve accuracy of displaying battery power. The method includes acquiring a power increase of a battery according to a preset time interval when the battery enters a charging state, where the battery has completed discharging before entering the charging state, acquiring power stored in the battery and an open circuit voltage OCV of the battery at a time when the acquired power increase of the battery reaches a preset threshold, generating an Open Circuit Voltage-State Of Capacity (OCV-SOC) curve according to the acquired power stored in the battery and the acquired OCV when the battery completes charging, and displaying the battery power according to the generated OCV-SOC curve.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: July 9, 2019
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Guanglin Wang
  • Patent number: 10330817
    Abstract: A method for generating a porosity log for a reservoir in an organic shale. The method includes receiving data representing one or more parameters in a reservoir in an organic shale. At least one of the parameters includes porosity. By stochastically inverting the data, a distribution of porobodon features is estimated that matches an observed pulse decay curve. The porosity data relates to petrophysical restrictions on at least one of the porobodon features.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 25, 2019
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: George A. Bordakov, David F. Allen
  • Patent number: 10319638
    Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10304998
    Abstract: A light emitting diode (LED) chip can include: a first pattern region having one or more curved parts; and a second pattern region at least partially surrounding the first pattern region. The first pattern region can include a first conductive type nitride-based semiconductor layer, an active layer, a second conductive type nitride-based semiconductor layer, a top electrode layer, and a top bump layer stacked over a substrate, the second pattern region can include a first conductive type nitride-based semiconductor layer, a bottom electrode layer, and a bottom bump layer stacked over the substrate, and the first pattern region can include one or more protrusion patterns formed in the one or more curved part.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 28, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Chang Hoon Kim, Sang Min Kim, Chi Hyun In, Hong Suk Cho, Dae Seok Park
  • Patent number: 10290702
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Michael A. Stuber, Stuart B. Molin, Jacek Korec, Boyi Yang
  • Patent number: 10290703
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 10283551
    Abstract: A back-illuminated solid-state imaging element includes a semiconductor substrate which has a front surface and a back surface provided with a recess, and in which a thinned section, which is a bottom section of the recess, is an imaging area, a signal read-out circuit formed on the front surface of the semiconductor substrate, a boron layer formed on at least the back surface of the semiconductor substrate and a lateral surface of the recess, a metal layer formed on the boron layer, and provided with an opening opposing a bottom surface of the recess, and an anti-reflection layer formed on the bottom surface of the recess.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 7, 2019
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Masaharu Muramatsu, Hisanori Suzuki, Yasuhito Yoneta, Shinya Otsuka, Hirotaka Takahashi
  • Patent number: 10276520
    Abstract: A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 30, 2019
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Zeng Li, Shou-Yu Hong, Jian-Hong Zeng
  • Patent number: 10242954
    Abstract: Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a magnetic mold resin that covers the surface of the substrate so as to embed the electronic component therein, the magnetic mold resin comprising a composite magnetic material containing a thermosetting resin material and a magnetic filler; and a laminated film including at least a metal film and a magnetic film, the laminated film covering at least an top surface of the magnetic mold resin. The metal film is connected to the power supply pattern, and the magnetic film has a higher effective permeability than that of the magnetic mold resin.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 26, 2019
    Assignee: TDK CORPORATION
    Inventor: Kenichi Kawabata
  • Patent number: 10229852
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 10224215
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10224267
    Abstract: A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching element are fixed on a second substrate. An upper arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. The lower arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shintaro Araki, Mitsunori Aiko, Takaaki Shirasawa, Khalid Hassan Hussein
  • Patent number: 10211250
    Abstract: The present disclosure relates to a solid-state image sensor and an electronic device enabling prevention of entrance of incident light from adjacent pixels and suppression of color mixture, decrease in resolution, and decrease in sensitivity. In a solid-state image sensor according to one aspect of the present disclosure, each pixel includes: these different photoelectric conversion parts configured to perform photoelectric conversion of light of a first wavelength of light of a second wavelength and a third wavelength respectively. An electrode wiring provided at a boundary of adjacent pixels, horizontally connects an electrode of at least one of the photoelectric conversion parts in one of the adjacent pixels with an electrode of the corresponding one of the photoelectric conversion parts in another of the adjacent pixels and vertically connects with an electrode of at least one of the photoelectric conversion parts of each of the pixels.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 19, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Ryosuke Matsumoto, Masahiro Joei
  • Patent number: 10177073
    Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
  • Patent number: 10177222
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 8, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yong-sik Won, Sang-uk Lee