Abstract: A method for manufacturing a display substrate includes: fabricating a first functional structure on a first side of a common substrate, and fabricating a second functional structure on a second side of the common substrate; fabricating a via hole in an edge region of the common substrate; and fabricating a conductive connection portion in the via hole, a first end of the conductive connection portion on the first side extending out of the via hole and coupled to a first functional pattern in the first functional structure, and a second end of the conductive connection portion on the second side extending out of the via hole and coupled to a second functional pattern in the second functional structure. The method provided in embodiments of the present disclosure is applied to the manufacturing of a display substrate.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate, a semiconductor device, an underfill element, and a groove. The semiconductor device is bonded to the surface of the package substrate through multiple electrical connectors. The underfill element is formed between the semiconductor device and the surface of the package substrate to surround and protect the electrical connectors. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The groove is formed in the fillet portion and spaced apart from the periphery of the semiconductor device.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: A display device may include a display substrate, an encapsulation substrate, and a sealing member. The display substrate may include a pixel defining layer. The sealing member may include a first portion having an inner portion between the display substrate and the encapsulation substrate and overlapping an edge portion of the pixel defining layer and an outer portion extending from the inner portion and located outside the inner portion; and a second portion between the outer portion and the display substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.

Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

Abstract: Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.

Abstract: A method of manufacturing a light emitting element includes forming an n-side electrode at a lateral surface of an n-type semiconductor layer so as not to cover a light extraction surface. Using a portion of a silicon substrate left on an n-type semiconductor layer as a mask, an insulating film formed at a lateral surface of a semiconductor layered body is removed, to expose a lateral surface of the n-type semiconductor layer and a lateral surface of a resin layer. An n-side electrode positioned between the lateral surface of the n-type semiconductor layer and the lateral surface of the resin layer and connected to the exposed lateral surface of the n-type semiconductor layer is formed. Thereafter, the portion of the silicon substrate is removed, to expose the n-type semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a source region and a drain region in a semiconductor substrate, and a bit line over the source region. The semiconductor device also includes a first epitaxial structure over the drain region, and a capacitor contact over the first epitaxial structure. A bottom surface of the capacitor contact is higher than a bottom surface of the bit line.

Abstract: The present disclosure relates to a method for preparing a semiconductor device. The method includes forming a source region and a drain region in a semiconductor substrate, and forming a bit line over the source region. The method also includes growing a first epitaxial structure over the drain region. A top surface of the first epitaxial structure is higher than a bottom surface of the bit line. The method further includes forming a capacitor contact over the first epitaxial structure.

Abstract: Radiation detecting-structures and fabrications methods thereof are presented. The methods include, for instance: providing a substrate, the substrate including at least one trench extending into the substrate from an upper surface thereof; and epitaxially forming a radiation-responsive semiconductor material layer from one or more sidewalls of the at least one trench of the substrate, the radiation-responsive semiconductor material layer responding to incident radiation by generating charge carriers therein. In one embodiment, the sidewalls of the at least one trench of the substrate include a (111) surface of the substrate, which facilitates epitaxially forming the radiation-responsive semiconductor material layer. In another embodiment, the radiation-responsive semiconductor material layer includes hexagonal boron nitride, and the epitaxially forming includes providing the hexagonal boron nitride with an a-axis aligned parallel to the sidewalls of the trench.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

Abstract: An organic light-emitting display apparatus includes: a substrate; first and second pixel electrodes on the substrate and spaced from each other; an insulating layer between the first and second pixel electrodes, the insulating layer covering ends of the first and second pixel electrodes, and having a step height difference; an auxiliary electrode on the insulating layer; first and second intermediate layers on the first and second pixel electrodes, the first and second intermediate layers being spaced from each other, and including first and second light-emitting layers, respectively; first and second opposite electrodes on the first and second intermediate layers, the first and second opposite electrodes being spaced from each other, and in contact with the auxiliary electrode; and first and second passivation layers on the first and second opposite electrodes, the first and second passivation layers being spaced from each other, and covering the first and second opposite electrodes, respectively.