Patents Examined by Kenneth Parker
  • Patent number: 9935090
    Abstract: An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers (RDLs) on the first die and the first molding compound. The device further includes a device package comprising a plurality of second dies, wherein the device package is bonded to an opposing surface of the one or more first RDLs as the first die and the first molding compound. A package substrate is bonded to the opposing surface of the one or more first RDLs. The package substrate is electrically connected to the first die and the plurality of second dies.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 9922878
    Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 20, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: De Yuan Xiao, Guo Qing Chen, Roger Lee
  • Patent number: 9913338
    Abstract: The present application provides a light-emitting device comprising a first light-emitting diode group; a second light-emitting diode group electrically connected to the first light-emitting diode group in parallel; and a temperature compensation element electrically connected to the second light-emitting diode group in series; and a first switch device connected between the second light-emitting diode group and the temperature compensation element.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: March 6, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Mao Liu, Zong-Xi Chen, Min-Hsun Hsieh, Chien-Yan Wang
  • Patent number: 9899408
    Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hwan Son, Young-Woo Park, Jae-Duk Lee
  • Patent number: 9893259
    Abstract: A light emitting device may include a substrate; a body which is disposed on the substrate and has a first hole having a predetermined size and a light emitting chip which is disposed within a cavity formed by the substrate and the first hole of the body. A cap may be disposed on the body and may have a second hole having a predetermined size. A transparent window may be disposed in the second hole. A lower portion of the cap is divided into a first surface and a second surface more projecting downwardly than the first surface, and at least a portion of the first surface is attached and fixed to the body.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 13, 2018
    Assignee: LG Innotek Co., Ltd.
    Inventors: Byung Mok Kim, Hiroshi Kodaira, Su Jung Jung, Bo Hee Kang, Young Jin No, Yuichiro Tanda, Satoshi Ozeki
  • Patent number: 9882032
    Abstract: A method includes forming isolation features on a substrate, thereby defining an active region on the semiconductor substrate; recessing the active region to form a fin trench; forming a fin feature on the fin trench by growing a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer; performing a first recessing process; forming a dummy gate stack over the fin feature and the isolation feature; performing a thermal oxidation process to selectively oxidize the first semiconductor layer to form a semiconductor oxide feature on sidewalls of the first semiconductor layer; performing a second recessing process such that a portion of the isolation feature is recessed to below the second semiconductor layer, resulting in a dented void overlying the semiconductor oxide feature and underlying the second semiconductor layer; and forming a gate stack including a gate dielectric layer extending to the dented void.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H Diaz
  • Patent number: 9871045
    Abstract: A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 16, 2018
    Assignee: HYNIX SEMICONDUCTOR INC.
    Inventors: Seung-Jin Yeom, Noh-Jung Kwak, Chang-Heon Park, Sun-Hwan Hwang
  • Patent number: 9859206
    Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo
  • Patent number: 9859372
    Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: January 2, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Li Liu, Xianyong Pu, Guangli Yang, Gangning Wang, ChiChung Tai, Hong Sun
  • Patent number: 9843010
    Abstract: Organic EL elements are configured so that at least a hole injection layer and a light-emitting layer are laminated between a first electrode and a second electrode, and a bank defines an area in which the light-emitting layer is to be formed. An inner portion of the hole injection layer is depressed to define a recess. An upper peripheral edge of the recess is covered with a part of the bank.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: December 12, 2017
    Assignee: JOLED INC.
    Inventor: Seiji Nishiyama
  • Patent number: 9837459
    Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Keiichiro Kashihara
  • Patent number: 9831394
    Abstract: An optoelectronic semiconductor component is provided, having a connection carrier (2), an optoelectronic semiconductor chip (1), which is arranged on a mounting face (22) of the connection carrier (2), and a radiation-transmissive body (3), which surrounds the semiconductor chip (1), wherein the radiation-transmissive body (3) contains a silicone, the radiation-transmissive body (3) has at least one side face (31) which extends at least in places at an angle ? of <90° to the mounting face (22) and the side face (3) is produced by a singulation process.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: November 28, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Binder, Alexander Linkov, Thomas Zeiler, Peter Brick
  • Patent number: 9831140
    Abstract: A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits. The wafer further includes a plurality of dielectric layers formed in the at least one scribe line having a process control monitor (PCM) pad structure formed therein, the PCM pad structure having: a plurality of metal pads interconnected by a plurality of conductive vias. The PCM pad further includes a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate. Additionally, the PCM pad includes an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
  • Patent number: 9825046
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu
  • Patent number: 9806026
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9806051
    Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 31, 2017
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 9799525
    Abstract: A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (Shanghai) CORP.
    Inventors: Wenbo Wang, Hanming Wu
  • Patent number: 9793289
    Abstract: A non-volatile memory device includes a conductive layer, a first electrode layer provided side by side with the conductive layer in a first direction, a second electrode layer provided between the conductive layer and the first electrode. At least a part of the second electrode on the conductive layer side has a work function smaller than a work function of the first electrode. The device further includes a first channel body extending through the first electrode layer in the first direction and a charge storage portion provided between the first electrode layer and the first channel body.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 17, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadayoshi Uechi, Masaki Kondo
  • Patent number: 9790088
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Patent number: 9786707
    Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Szu-An Wu