Patents Examined by Kevin L. Ellis
  • Patent number: 8250281
    Abstract: Data communications through a host Fiber Channel adapter (‘HFCA’) implemented with a computer that includes two or more logical partitions, each logical partition including a separate instance of an operating system, each instance of an operating system including an instance of a low-level, switched fabric input/output (‘I/O’) library, including establishing, in the HFCA by instances of the I/O library in two or more logical partitions and by the hypervisor, separate logical Fiber Channel adapters (‘LFCAs’) for at least two of the logical partitions, each LFCA including an association of an LFCA identifier with at least one range of I/O memory addresses in the address space of a logical partition and transferring, at the behest of application programs in the two or more logical partitions, data between the RAM of the logical partitions and the data storage devices through the LFCAs, the HFCA, and the Fiber Channel fabric.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ellen M. Bauman, Timothy J. Schimke, Lee A. Sendelbach, Joseph T. Writz
  • Patent number: 8244992
    Abstract: A method that includes, by one or more computer systems, determining a data retrieval rate policy based on at least one data retrieval rate parameter. The method also includes determining at least one storage subsystem performance parameter. The method further includes determining a fragmentation value based on the data retrieval rate policy and the at least one storage subsystem performance parameter. The method additionally includes determining a storage subsystem fragmentation of a first data object. The storage subsystem fragmentation includes fragmenting the first data object into a plurality of first data object fragments. The method also includes deduplicating the first data object based on the fragmentation value and the storage subsystem fragmentation.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: August 14, 2012
    Inventor: Stephen P. Spackman
  • Patent number: 8245002
    Abstract: Call stack protection, including executing at least one application program on the one or more computer processors, including initializing threads of execution, each thread having a call stack, each call stack characterized by a separate guard area defining a maximum extent of the call stack, dispatching one of the threads of the process, including loading a guard area specification for the dispatched thread's call stack guard area from thread context storage into address comparison registers of a processor; determining by use of address comparison logic in dependence upon a guard area specification for the dispatched thread whether each access of memory by the dispatched thread is a precluded access of memory in the dispatched thread's call stack's guard area; and effecting by the address comparison logic an address comparison interrupt for each access of memory that is a precluded access of memory in the dispatched thread's guard area.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E Attinella, Mark E Giampapa, Thomas M. Gooding
  • Patent number: 8239633
    Abstract: A coherence controller in hardware of an apparatus in an example detects conflicts on coherence requests through direct, non-broadcast employment of signatures that: summarize read-sets and write-sets of memory transactions; and provide false positives but no false negatives for the conflicts on the coherence requests. The signatures comprise fixed-size representations of a substantially arbitrary set of addresses for the read-sets and the write-sets of the memory transactions.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 7, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: David A. Wood, Mark D. Hill, Michael M. Swift, Michael R. Marty, Luke Yen, Kevin E. Moore, Jayaram Bobba, Haris Volos
  • Patent number: 8225033
    Abstract: A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunications system are further disclosed.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Brian Johnson
  • Patent number: 8140785
    Abstract: Provided are a method, system, and article of manufacture for updating metadata in a logical volume associated with a storage controller. A data structure is generated indicating data units in a volume whose metadata is to be updated. An operation is initiated to update the metadata for data units indicated in the data structure. Indication is made in the data structure that the metadata for one data unit has been updated in response to updating the metadata for the data unit. An Input/Output (I/O) request is received to one data unit in the volume while the metadata for the data units indicated in the data structure is being updated. A determination is made, in response to the I/O request, from the data structure whether the metadata for the requested data unit was updated. The metadata for the requested data unit is updated in response to determining that the metadata for the requested data unit has not been updated. The I/O request is executed against the requested data unit.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Kalos, Robert Akira Kubo
  • Patent number: 8086809
    Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: December 27, 2011
    Assignee: CommVault Systems, Inc.
    Inventors: Anand Prahlad, Randy De Meno, Jeremy A. Schwartz, James J. McGuigan
  • Patent number: 8069317
    Abstract: An enhanced mechanism for the allocation, organization and utilization of high performance block storage metadata provides a stream of data (e.g., in a server system, storage system, DASD, etc.) that includes a sequence of fixed-size blocks which together define a page. Each of the fixed-size blocks includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. Each footer in the confluence of footers has space available for application metadata, which are provided as one or more information units. At least one of the footers includes a Checksum field containing a checksum that covers at least the confluence of footers. This approach is advantageous in that it provides data integrity protection, protects against stale data, and significantly increases the amount of metadata space available for application use.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: November 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Wayne Boyd, Jeffrey William Palm, George Oliver Penokie
  • Patent number: 8065570
    Abstract: Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having outputs coupled to enable inputs of the numerous DCI modules, where operating the IC in a test mode configures the control circuit to selectively couple a control signal to the enable terminals of the numerous DCI modules. One DCI module of the numerous DCI modules can be enabled at a time facilitating testing of the configurable impedances of the I/O terminals.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: November 22, 2011
    Assignee: Xilinx, Inc.
    Inventors: Tuyet Ngoc Simmons, Madan Mohan Patra
  • Patent number: 8046546
    Abstract: A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 25, 2011
    Assignee: AGIGA Tech
    Inventor: Ronald H Sartore
  • Patent number: 8037252
    Abstract: Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventor: Farnaz Toussi
  • Patent number: 8019959
    Abstract: A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: September 13, 2011
    Assignee: Marvell World Trade Ltd.
    Inventors: Zining Wu, Lau Nguyen, Pantas Sutardja, Chi-Kong Lee, Tony Yoon
  • Patent number: 8019942
    Abstract: A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: September 13, 2011
    Assignee: SanDisk Technologies, Inc.
    Inventors: Eliyahou Harari, Yoram Cedar, Wesley G. Brewer, Yosi Pinto, Reuven Elhamias, Michael Holtzman
  • Patent number: 8019965
    Abstract: The present invention provides for a method for managing the storage of data in a computing system that includes a data processor and local physical storage, involving the steps of: defining a virtual storage volume for access by the data processor, the data processor including a local storage pool mapped to the local physical storage and a remote storage pool mapped to physical storage at a remote site, and the virtual storage volume being overallocated with respect to the local storage pool; and migrating data between the local storage pool and the remote storage pool according to a defined migration policy.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Christopher B. Beeken, Stephanie Machleidt, Simon Walsh
  • Patent number: 8015362
    Abstract: A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gregory W. Alexander, Christian Jacobi, Barry W. Krumm, Chung-Lung Kevin Shum, Aaron Tsai
  • Patent number: 8010747
    Abstract: Embodiments of the present invention provide methods and systems for efficiently tracking evicted or non-resident pages. For each non-resident page, a first hash value is generated from the page's metadata, such as the page's mapping and offset parameters. This first hash value is then used as an index to point one of a plurality of circular buffers. Each circular buffer comprises an entry for a clock pointer and entries that uniquely represent non-resident pages. The clock pointer points to the next page that is suitable for replacement and moves through the circular buffer as pages are evicted. In some embodiments, the entries that uniquely represent non-resident pages are a hash value that is generated from the page's inode data.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 30, 2011
    Assignee: Red Hat, Inc.
    Inventor: Henri Han van Riel
  • Patent number: 8010763
    Abstract: Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: William J. Armstrong, Orran Y. Krieger, Cathy May, Michal Ostrowski, Randal C. Swanberg
  • Patent number: 8010759
    Abstract: Redirecting a data object such as a file block extent. The data object can be redirected from a first memory block to a second memory block, wherein the second memory block includes a copy of modified data of the first memory block. The redirection may occur in response to a request to modify data of the data object. Redirection preserves the prior version of the data object stored in the first memory block to enable restoration of the data object if needed. In one embodiment, a first data object is mapped to a first memory block. A copy of data contents of the first memory block is created. Thereafter, data contained within the copy is modified in accordance, for example, with a request to write data to the first data object. The modified copy is stored in a second memory block, and the first data object is mapped to the second memory block.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 30, 2011
    Assignee: Symantec Operating Corporation
    Inventors: Timothy R. Coulter, Raghu Krishnamurthy, Par A. Botes
  • Patent number: 8006063
    Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyuki Mimatsu, Masayuki Yamamoto
  • Patent number: RE42648
    Abstract: A source block (B0) and the logical page number (“8”) of a write target page are identified from the logical address of the write target page. Data objects (DN8, DN9, . . . , DN12) to be written, which a host stores in a page buffer (2), are written into the data areas (DA) of the pages (Q0, Q1, . . . , Q4) of a destination block (Bn), starting from the top page (Q0) in sequence. The logical page number (“8”) of the write target page is written into the redundant area (RA) of the top page (Q0). The physical page number (“6=8?2”) of the write target page is identified, based on the logical page number (“8”) of the write target page and the page offset (“2”) of the source block (B0). When notified by the host of the end of the sending of the data objects (DN8, . . . , DN12), the data items (D13, . . . , D31, D0, D1, . . . , D7) in the source block (B0) are transferred to the pages (Q5, Q6, . . .
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: August 23, 2011
    Assignee: PANASONIC Corporation
    Inventors: Yoshihisa Inagaki, Toshiyuki Honda