Patents Examined by Kevin L. Ellis
  • Patent number: 7971023
    Abstract: In order to maintain a memory system's performance levels to its end-of-life, latency threshold level(s) are specified and associated with different memory system operating parameters. In one embodiment, the memory system monitors and gathers performance statistics in real time, and in accordance with specific memory transfer sizes. A current latency level can be dynamically calculated using the performance statistics and compared to previously established latency threshold levels. If the current latency level is greater than or equal to a specific latency threshold level, the memory system's configuration setting can be adjusted according to the operating parameters associated with the latency threshold level to offset the increased latency.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 28, 2011
    Assignee: SanDisk Corporation
    Inventors: Steven S. Cheng, Stephen Tam
  • Patent number: 7971003
    Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 28, 2011
    Assignee: STMicroelectronics SA
    Inventors: Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
  • Patent number: 7971002
    Abstract: Methods and systems for maintaining instruction coherency in a translation-based computer system architecture are described. A translation coherence cache memory can be used to store a memory page reference that identifies a memory page. The cache memory also stores a permission bit corresponding to the memory page reference. The permission bit indicates whether the memory page comprises code that has been translated into another form.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 28, 2011
    Inventors: Guillermo Rozas, David Dunn
  • Patent number: 7971001
    Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to identify an object that is eligible for eviction from said region of cache. The sorting method includes identifying an object for eviction that is cached in the region of cache and that has been used least recently compared to other objects that are cached in the region of cache.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 28, 2011
    Assignee: SAP AG
    Inventors: Petio G. Petev, Michael Wintergerst
  • Patent number: 7971000
    Abstract: The invention concerns a method and a system for maintaining consistency of a cache memory, accessible by multiple independent processes. The processes can share common data. The processes perform simultaneous data searching operations optionally followed by providing the data to the processes, a removal of same or an insertion of new data. The searching, removal and insertion operations, are comprehensively executed once they have been initiated by the independent processes. They are executed excluding one another when they must operate on common data. The removal or insertion operations are each completely reversible. In that context, the invention provides that the operations for providing, removing or inserting the data have a finite or bound duration of execution so as to prevent any locking.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: June 28, 2011
    Assignee: Amadeus s.a.s.
    Inventors: Frédérick Ros, Rudy Daniello, Luc Isnardy, Claudine Reynaud, Wayne Rubenstein
  • Patent number: 7971011
    Abstract: A remote copy method for copying data within a first storage apparatus to a second storage apparatus via a network, includes transmitting data from the first storage apparatus in units of first buffer sets each formed by a plurality of first recording exclusive buffers within the first storage apparatus, and receiving the data by the second storage apparatus in units of second buffer sets each formed by a plurality of second recording exclusive buffers within the second storage apparatus, so as to maintain a sequence guarantee with respect to the data that is copied.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Furukawa, Hiroshi Okamoto
  • Patent number: 7966469
    Abstract: A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: June 21, 2011
    Assignee: Qimonda AG
    Inventors: Maurizio Skerlj, Anthony Sanders
  • Patent number: 7962700
    Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Luis Alfonso Lastras-Montano, Robert Brett Tremaine
  • Patent number: 7958306
    Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: June 7, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yuri Hiraiwa, Nobuhiro Maki, Takeyuki Imazu
  • Patent number: 7953929
    Abstract: A system, method, apparatus, and computer-readable medium are provided for expanding the data storage capacity of a virtualized storage system, such as a storage cluster. According to one method, maps are generated and stored that define a stripe pattern for storing data on the storage nodes of a storage cluster. The stripe pattern for each map is defined such that when a storage node is added to a cluster and the data is re-striped according to the new map, only the data that will subsequently reside in the new storage node is moved to the new storage cluster during re-striping. The stripe pattern may be further defined so that during re-striping no movement of data occurs between two storage nodes that existed in the cluster prior to the addition of the new storage node. The stripe pattern may be further defined such that during re-striping an equal amount of data is moved from each of the storage nodes that existed in the cluster prior to the addition of the new storage node to the new storage node.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: May 31, 2011
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Narayanan Balakrishnan, Ajit Narayanan, Vijayarankan Muthirisavenugopal
  • Patent number: 7953928
    Abstract: An apparatus and a method to make data sets conform to data management policies are presented. In one embodiment, the apparatus includes a conformance checker and a conformance engine. The conformance checker may be operable to compare a state of a data set against a data management policy associated with the data set to determine if the data set currently conforms to the data management policy. The conformance engine may then make the data set conform to the data management policy if the conformance checker determines that the data set currently violates the data management policy.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: May 31, 2011
    Assignee: Network Appliance, Inc.
    Inventors: Peter L. Smoot, Jim Holl, Sahn Lam, Anawat Chankhunthod
  • Patent number: 7953949
    Abstract: The present invention provides techniques, including a method and system, for relocating data between storage systems. In one embodiment of the present invention a host collects usage information from a plurality of storage systems, and determines the relocation destination LU for data stored in the LU to be relocated. The host alters an LU logical position name table that determines matching between the logical position names of data and LUs. It also carries out data relocation between storage subsystems by shifting data stored in an origin LU to be relocated to a destination LU. In another embodiment relocation of files is provided.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 31, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Arakawa, Kazuhiko Mogi, Yoshiaki Eguchi, Kouji Arai
  • Patent number: 7953952
    Abstract: The management server performs a release/non-release selection determining whether or not to release all of the real storage areas assigned to a virtual volume switched from a used target to an unused target. The management server exercises control to determine whether or not to release all of the real storage areas assigned to the specified virtual volume in accordance with the result of the release/non-release selection.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 31, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Hiroyuki Tanaka
  • Patent number: 7949847
    Abstract: A thin provisioning storage system is able to present a thin provisioned volume to a computer, such that the computer stores data to the volume as if storage space on disk drives was already allocated for the volume. Upon receiving a write request from the computer, in which the write request is directed to an area of the volume for which storage space on the disk drives has not yet been allocated, the storage system allocates new space on the disk drives. When allocating the new space, the storage system obtains a designated performance level for the volume, and determines a number of storage extents to be allocated to the volume based upon the determined performance level. The storage system also is able to take into account performance metrics for the disk drives and/or array groups when selecting locations from which to allocate the storage extents.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: May 24, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Atsushi Murase
  • Patent number: 7945727
    Abstract: A disk drive is disclosed including a disk comprising a plurality of refresh zones, and a head actuated over the disk. The disk drive further comprises control circuitry for receiving access commands from a host. The control circuitry refreshes a refresh zone in a plurality of segments with an interval between each segment, and processes at least one of the access commands during the interval between at least two of the segments, wherein a size of each segment and the interval ensures an average throughput of access commands received from the host does not fall below a first threshold.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: May 17, 2011
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael S. Rothberg, William B. Boyle, Chun Sei Tsai
  • Patent number: 7941628
    Abstract: A plurality of storage devices of a plurality of types is provided. A plurality of criteria is associated for each of the plurality of storage devices, based on characteristics of the plurality of storage devices, wherein the plurality of criteria can be used to determine whether a selected storage device is a compatibility spare for a storage device in a storage device array, and whether the selected storage device is an availability spare for the storage device in the storage device array. A determination is made by a spare management application, based on at least the plurality of criteria and at least one optimality condition, of a first set of storage devices selected from the plurality of storage devices to be allocated to a plurality of storage device arrays, and of a second set of storage devices selected from the plurality of storage devices to be allocated as spares for the plurality of storage device arrays.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Joseph Kalos, Robert Akira Kubo, Richard Anthony Ripberger
  • Patent number: 7941608
    Abstract: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 10, 2011
    Assignee: ARM Limited
    Inventors: Florent Begon, Philippe Luc, Elodie Charra, Nicolas Chaussade
  • Patent number: 7941604
    Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: May 10, 2011
    Assignee: Infineon Technologies AG
    Inventors: Raj Kumar Jain, Xiao Ni Wei, Pin Xing Lin
  • Patent number: 7941609
    Abstract: Described is a technology by which high latency problems with respect to web requests are reduced by having a web proxy server predict and pre-fetch content, in parallel, that is to be requested by a client. The web proxy analyzes a main web page requested by a client to predict subsequent client requests. The web proxy pre-fetches content before the client requests it, by making concurrent requests for the page's embedded objects that exceed the client's limited number of (e.g., two) connections. In one example, the web proxy sends HTTP requests substantially in parallel to a web server, thereby reducing overall latency. In another example, the web proxy server sends parallel requests to a remote web proxy coupled to a web server. The remote web proxy requests only a limited number of objects (e.g., two) at a time, but does so over fast (low latency) connections to the web server.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: May 10, 2011
    Assignee: Microsoft Corporation
    Inventor: Itai Almog
  • Patent number: 7937540
    Abstract: A device driver includes an access permitted directory storage unit and an access-permission determining unit. The access-permitted directory storage unit stores as an access-permitted directory an activation directory for a process that is allowed to access an S memory (private memory). The access-permission determining unit checks whether an activation directory for a process that has requested for access to the S memory matches the access-permitted directory. Based on the result, the access-permission determining unit determines whether to accept the access request.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Sonoda, Shigehiro Idani, Tomoyoshi Takebayashi, Akihiro Inomata, Gakuto Ozaki