Abstract: A motion image processing device for producing a representative static image based on motion image data recorded on a recording medium, comprising; acquiring image acquiring position information for specifying an image acquiring position in the motion image data, acquiring a reproduced image in the image acquiring position specified by the acquired image acquiring position information from the motion image data as a representative static image, and storing the acquired image acquiring position information on the recording medium so as to be associated with the information specifying the motion image data.

Abstract: A method for automatically determining performance problems in a computer system due to a metric indicating a current memory peak load in the computer system is disclosed.

Abstract: A storage apparatus includes a drive unit in which a logical unit is formed, and a controller unit for accessing the logical unit by controlling the drive unit according to an access request sent from a host apparatus. The storage apparatus issues a logical unit takeover request to the other storage apparatuses, allocates a logical unit of another storage apparatus that will accept the transfer of the logical volume to its own logical unit according to a takeover approval sent from other storage apparatuses in response to the takeover request, and thereafter migrates data of the own logical unit to a logical unit of another storage apparatus. Subsequently, the path is switched so that the access request from the host apparatus is given to one of the other storage apparatuses.

Abstract: In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

Abstract: To manage physical paths between a server system and a storage system and information about routing between virtual machines and virtual storage systems in an integrated fashion. A computer system of the present invention includes: a computer and a storage system that stores data, in which the computer includes first information for managing the first resource relating to the computer; and the storage system includes second information for managing the second resource provided in the storage system, and in which a relation between the virtual machine and the virtual storage system is defined based on the first information and the second information.

Abstract: An application may issue write operations intended for a SAN via a server cache. Monitoring of the SAN (e.g., the autonomous persistent cache of the storage arrays of the SAN), allows caching performance to be controlled by a write caching policy. The server cache memory may be increased, decreased or eliminated according to the write caching policy. In one embodiment, a storage volume manager may adjust the latency of write operations in the server cache. In some embodiments, the write caching policy may adapt and learn characteristics of the storage environment, which may include calibrated values for messaging timestamps.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: Each of memory cards can have a different type and can be in a plurality of statuses. The memory cards are managed by a file system and data is read/written from/to the memory cards via an access device. Each of the memory cards has a recording area in which data is recorded and managed by an independent file system, a state storage section for storing state assigned to each of combinations of the memory card type and status and being capable of uniquely identifying the combination, and card information storage sections the number of which is identical to the number of states the memory card can have, and which store physical characteristics concerning the recording area. The access device acquires from the memory card a state enable uniquely identifying the memory card type and status. According to the state acquired, the access device identifies the type and status of the memory card and executes processing in accordance with the memory card state.

Abstract: A system for increasing the efficiency of migrating, at least in part, a virtual machine from a source host to a destination host is described wherein the content of one or more portions of the address space of the virtual machine are each uniquely associated at the source host with a signature that may collide, absent disambiguation, with different content at the destination host. Code in both the source and destination hosts disambiguates the signature(s) so that each disambiguated signature may be uniquely associated with content at the destination host, and so that collisions with different content are avoided at the destination host. Logic is configured to determine whether the content uniquely associated with a disambiguated signature at the destination host is already present in the destination host memory, and, if so, to back one or more portions of the address space of the virtual machine having this content with one or more portions of the destination host memory already holding this content.

Abstract: The present invention in at least some embodiments relates to improved methods and systems for governing access to SAN data storage devices (or simply “SAN devices”) employed in SAN systems. In some embodiments, the method involves storing a list at a SAN device. The list can be an exclusion list identifying devices that are not allowed to access the SAN device. During normal operation, the SAN device automatically contacts the SAN (or a component of the SAN, such as a SAN switch) to determine the identities of new devices that have entered into communication with the SAN. The SAN device then automatically updates the exclusion list to include those new devices such that, without further instructions, the SAN device is not accessible by those new devices. The method further can relate to the setup and failure recovery of SAN devices employed in SAN systems.

Abstract: The present invention eliminates the possibility of problems with viruses, worms, identity theft, and other hazards that may result from the connection of a computer to the Internet. It does so by creating a new configuration of components within the computer. In addition to commonly used components, two new components are added. These are a secondary hard drive and a secondary random access memory. When the computer is connected to the Internet these secondary components are used in place of their primary counterparts. The primary hard drive is electronically isolated from the Internet, thus preventing Internet contamination of the primary hard drive.

Abstract: A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.

Abstract: There is provided a flash memory apparatus for storing data aggregate having a plurality of types of data in and reproduce the data aggregate from a flash memory via a plurality of ports. The flash memory apparatus includes a plurality of access request units configure to request to write data in one block of the flash memory by aligning a writing position of one block data with a page unit on a data type basis of the flash memory when the data classified by type that are inputted via the ports corresponding to the access request units on the one-to-one basis are stored to reach an amount relative to one block of the flash memory, and an access controller configured to write the data in the flash memory during time division allocated per port based on the requests incited by the respective access request units.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for performing a data subscribe operation at the consumer node, wherein the data subscribe operation records that a memory address is subscribed at the consumer node, a data publish mechanism for performing a data publish operation at the producer node, wherein the data publish operation sends data of the memory address from the producer node to the consumer node if the memory address is subscribed at the consumer node, and a communication network coupled to the producer node and the consumer node for enabling communicating between the producer node and the consumer node.

Abstract: A system that, at a process checkpoint, pauses the process to copy the system state for the process and then copies pages of the process in memory to disk storage while the process continues to run. When a write to a page by the process is to occur that requires a translation from a virtual address to a physical address the write is intercepted. The page that is being modified is duplicated and then the process is allowed to modify the page and continue. The duplicate page is then stored as part of the checkpoint copy.

Abstract: A virtual storage system control apparatus, a virtual storage system control program and a virtual storage system control method can move one or more than one virtual volumes without suspending the services being provided. The virtual storage system control apparatus comprises a plurality of storage device control sections that assign virtual volumes to the storage devices of the virtual storage clusters, generate information on the virtual volumes, set up a link between the virtual volumes of the own virtual storage clusters and the virtual volumes of other virtual storage clusters by way of the network and copy data on the basis of the link and a management node that directs a move of a virtual volume by having the link set up according to the information on the virtual volumes.

Abstract: A storage system includes a plurality of disk apparatuses configuring a plurality of RAID groups, a spare disk apparatus, and a controller. The controller is adapted to copy data stored in a disk apparatus, whose error count exceeds a first threshold, to the spare disk apparatus. If an error count of a disk apparatus included in a RAID group exceeds a second threshold which is lower than the first threshold, the controller is adapted to check error counts of other disk apparatuses included in the same RAID group. If any of the error counts of the other disk apparatuses included in the same RAID group exceeds the second threshold, the controller is adapted to change the first value of the first disk apparatus and the other disk apparatuses included in the same RAID group.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.