Patents Examined by Kevin M. Picardat
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Patent number: 10243061Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.Type: GrantFiled: November 15, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
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Patent number: 10236469Abstract: A display device includes a display panel, a driving circuit board, and an electronic connector. The electronic connector connects the display panel and the driving circuit board. The driving circuit board is configured with a first wire, a second wire, a third wire, a fourth wire and a fifth wire arranged in order. The first wire, the second wire, the third wire and the fifth wire extend to the electronic connector and connect to the display panel. A first convergence point of the second wire and the third wire is located on the electronic connector, and a second convergence point of the fourth wire and the third wire is located on the driving circuit board. A detection method of the display device is also disclosed.Type: GrantFiled: June 13, 2017Date of Patent: March 19, 2019Assignee: INNOLUX CORPORATIONInventors: Chia-Yuan Chang, Chia-Chieh Fan
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Patent number: 10230035Abstract: Light emitting diode packages as disclosed herein include a monolithic chip including at least a first and a second light emitting diode (LED) that are electrically coupled in series, wherein the first and the second LEDs each include at least one electrical terminal configured to be electrically coupled to a power source. The monolithic chip is mounted onto a connection substrate having first and second landing pads formed from metallic material and electrically isolated from each other. The monolithic chip is mounted to the connection substrate such that the electrical terminal of the first LED is electrically connected to the first landing pad and the electrical terminal of the second LED is electrically connected to the second landing pad. In an example, the monolithic chip includes a third and a fourth LED electrically coupled to each other in series, and electrically coupled to the first and second LEDs in parallel.Type: GrantFiled: December 22, 2017Date of Patent: March 12, 2019Assignee: Bridgelux, Inc.Inventor: Vladimir A. Odnoblyudov
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Patent number: 10224409Abstract: The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy.Type: GrantFiled: February 3, 2016Date of Patent: March 5, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Yongchao Huang
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Patent number: 10214415Abstract: A silicon carbide based MOS integrated circuit is monolithically integrated with a suspended piezoelectric aluminum nitride member to form a high-temperature-capable hybrid MEMS-over-MOS structure. In the integrated structure, a post-MOS passivation layer of silicon carbide is deposited over the MOS passivation and overlain by a structural layer of the MEMS device. Electrical contact to refractory metal conductors of the MOS integrated circuit is provided by tungsten vias that are formed so as to pass vertically through the structural layer and the post-MOS passivation layer.Type: GrantFiled: March 2, 2018Date of Patent: February 26, 2019Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Benjamin Griffin, Scott D. Habermehl, Peggy J. Clews
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Patent number: 10217922Abstract: Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions. An advantageous coincidence of material properties makes possible a wide variety of unique microstructures that are easily applied for the fabrication of device structures in general. As an example, a direct bond process is applied to fabricate thermoelectric semiconductor thick films on substrates by printing and subsequent thermal processing to form unique microstructures which can be densified. Bismuth and antimony telluride are directly bonded to flexible nickel substrates.Type: GrantFiled: May 27, 2016Date of Patent: February 26, 2019Assignee: BERKEN ENERGY LLCInventor: Ronald R. Petkie
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Patent number: 10217698Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: GrantFiled: December 19, 2016Date of Patent: February 26, 2019Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
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Patent number: 10211208Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.Type: GrantFiled: June 26, 2015Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Tahir Ghani, Willy Rachmady, Chandra S. Mohapatra, Jack T. Kavalieros, Glenn A. Glass
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Patent number: 10211404Abstract: A high-performance organic electroluminescence device and an electronic equipment provided with the organic electroluminescence device are provided. Also, a compound for achieving the organic electroluminescence device and the electronic equipment is provided. Specifically, a compound having a specific structure having a triphenylene skeleton, an organic electroluminescence device using the compound and an electronic equipment provided with the organic electroluminescence device are provided.Type: GrantFiled: January 29, 2015Date of Patent: February 19, 2019Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Masahiro Kawamura, Yumiko Mizuki, Hirokatsu Ito, Tomoharu Hayama, Tasuku Haketa
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Patent number: 10204853Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.Type: GrantFiled: June 13, 2017Date of Patent: February 12, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masahiro Matsumoto, Akira Yajima, Kazuyoshi Maekawa
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Patent number: 10204917Abstract: In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.Type: GrantFiled: January 31, 2017Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Yang, Chung-Jen Huang
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Patent number: 10205052Abstract: A semiconductor stacking structure according to the present invention comprises: a monocrystalline substrate which is disparate from a nitride semiconductor; an inorganic thin film which is formed on a substrate to define a cavity between the inorganic thin film and the substrate, wherein at least a portion of the inorganic thin film is crystallized with a crystal structure that is the same as the substrate; and a nitride semiconductor layer which is grown from a crystallized inorganic thin film above the cavity. The method and apparatus for separating a nitride semiconductor layer according the present invention mechanically separate between the substrate and the nitride semiconductor layer. The mechanical separation can be performed by a method of separation of applying a vertical force to the substrate and the nitride semiconductor layer, a method of separation of applying a horizontal force, a method of separation of applying a force of a relative circular motion, and a combination thereof.Type: GrantFiled: July 13, 2015Date of Patent: February 12, 2019Assignee: Seoul National University R&DB FoundationInventors: Eui-Joon Yoon, Dae-Young Moon, Jeong-Hwan Jang, Yongjo Park, Duk-Kyu Bae
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Patent number: 10199592Abstract: A highly reliable micromachine, display element, or the like is provided. As a micromachine or a transistor including the micromachine, a transistor including an oxide semiconductor in a semiconductor layer where a channel is formed is used. For example, a transistor including an oxide semiconductor is used as at least one transistor in one or a plurality of transistors driving a micromachine.Type: GrantFiled: October 20, 2015Date of Patent: February 5, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takayuki Ikeda, Yoshiyuki Kurokawa
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Patent number: 10199295Abstract: A display panel and a method for forming the same are disclosed. The display panel includes a first substrate and a second substrate arranged opposite to each other. An integrated circuit (IC) is arranged at a non-display region of the first substrate, and at least one supporting component is arranged beyond a portion of the non-display region where the IC is arranged. A thickness of the at least one supporting component is larger than a thickness of the IC.Type: GrantFiled: February 1, 2016Date of Patent: February 5, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Fan Yang, Kun Guo, Yuqing Yang, Qi Liu, Bo Zhang, Fei Chen, Tianyi Cheng, Zihua Li, Yan Wu, Jin Yang, Liman Peng, Chao Kong
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Patent number: 10192819Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.Type: GrantFiled: November 16, 2017Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel Chanemougame, Lars Liebmann, Ruilong Xie
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Patent number: 10186631Abstract: Squared-off semiconductor coatings for quantum dots (QDs) and the resulting quantum dot materials are described. In an example, a semiconductor structure includes a quantum dot structure having an outermost surface. A crystalline semiconductor coating is disposed on and completely surrounds the outermost surface of the quantum dot structure. The crystalline semiconductor coating has a geometry with squared-off ends.Type: GrantFiled: May 14, 2015Date of Patent: January 22, 2019Assignee: OSRAM Opto Semiconductors GmbHInventors: Matthew J. Carillo, Steven Hughes
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Patent number: 10186403Abstract: A tablet for a plasma coating system having a first part that includes a first material having a first sublimation point at a first pressure and a second part that is disposed on the first part and comprises a second material having a second melting point at the first pressure, wherein the second melting point is lower than the first sublimation point.Type: GrantFiled: October 5, 2015Date of Patent: January 22, 2019Assignee: Samsung Display Co., Ltd.Inventors: Hun Kim, Jin-Woo Park
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Patent number: 10181482Abstract: According to an embodiment of the present disclosure, a method for manufacturing the array substrate includes forming a first transparent conductive layer and a metallic layer successively on a base substrate, and forming a gate electrode, a source electrode, a drain electrode and a first transparent electrode by one patterning process.Type: GrantFiled: February 24, 2016Date of Patent: January 15, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhengliang Li, Qi Yao, Bin Zhang, Zhanfeng Cao, Wei Zhang, Xuefei Sun, Bin Zhou, Jincheng Gao
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Patent number: 10180608Abstract: An array substrate and a liquid crystal display apparatus are disclosed. The array substrate includes: a glass substrate; a light-shielding metallic layer mounted having a first region and a second region; a first insulating layer; a thin-film transistor; a pixel electrode layer; a common electrode layer electrically connected to the light-shielding metallic layer. A storage capacitor is formed between the second region and a drain electrode of the thin-film transistor. The array substrate has an advantage of increasing the storage capacitance of liquid crystal display apparatus and therefore enhancing display performance.Type: GrantFiled: May 17, 2016Date of Patent: January 15, 2019Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Cong Wang
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Patent number: 10181500Abstract: Disclosed are a display device and a method of manufacturing the same, which prevent a reduction in an aperture ratio and occurrence of color mixing caused by a process error of a black matrix and a color filter. The display device includes a plurality of color filters, an inorganic layer covering the plurality of color filters, and a black matrix disposed on the inorganic layer between the plurality of color filters.Type: GrantFiled: December 27, 2016Date of Patent: January 15, 2019Assignee: LG Display Co., Ltd.Inventor: JongSung Kim