Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

Abstract: A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.

Abstract: The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

Abstract: A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

Abstract: Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line.

Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.

Abstract: An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.

Abstract: Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

Abstract: A semiconductor device includes a transistor, a bit line and a bit-line via structure. The transistor is located in a transistor layer, and has a source contact and a drain contact. The bit line is electrically connected to one of the source contact and the drain contact. The bit-line via structure is located in the transistor layer, and electrically interconnects the bit line and a periphery device.

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

Abstract: A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

Abstract: A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors.

Abstract: Systems, methods and apparatus are provided for depositing alternating layers of dielectric material and sacrificial material in repeating iterations to form a vertical stack, forming a plurality of vertical openings through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack, patterning the pillar columns to expose a location to form a channel region, selectively removing a portion of the sacrificial material to form first horizontal openings in the first horizontal direction in the sidewalls of the elongated vertical, pillar columns, and depositing a channel material in the first horizontal openings to form the channel region within the sidewalls for the horizontally oriented access devices.

Abstract: A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.