Patents Examined by Khaja Ahmad
  • Patent number: 11855171
    Abstract: A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Sheng-Han Yi, Chen-Hsuan Lu
  • Patent number: 11854889
    Abstract: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: December 26, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11848399
    Abstract: Provided are a method of manufacturing a display apparatus and the display apparatus. The method includes forming an emissive layer and a driving layer on a first area of a substrate, forming an exposure line electrically connected to the driving layer, on a second area of the substrate, and forming a color conversion layer on the driving layer by emitting light from the emissive layer using the exposure line.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiho Kong, Junhee Choi, Deukseok Chung, Junsik Hwang
  • Patent number: 11843035
    Abstract: Semiconductor devices including structures of active region are disclosed. An example semiconductor device according to the disclosure includes a substrate, a layer on the substrate and a dielectric layer on the layer. The layer includes an interface in contact with the dielectric layer. The interface includes a first portion on a surface of the layer and a second portion perpendicular to the first portion.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Moeko Kawana, Yoshikazu Moriwaki
  • Patent number: 11842938
    Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 11837668
    Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 5, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro Tomita, Tomohiro Hirai, Shintaro Okamoto, Kentaro Eda, Takashi Watanabe, Kazuki Yamaguchi, Norikazu Kasahara, Kohei Suzuki
  • Patent number: 11839119
    Abstract: A display device includes a display substrate including a plurality of first pads arranged in a first pad area and a plurality of second pads arranged in a second pad area, wherein the first pads and the second pads are arranged in different rows from each other, a circuit board including first circuit pads facing the first pads, respectively, and second circuit pads facing the second pads, respectively, and an adhesive member disposed between the display substrate and the circuit board and including an adhesive layer and a plurality of conductive balls distributed in the adhesive layer. Here, a first density of first conductive balls overlapping the first pad area among the conductive balls is greater that a second density of second conductive balls overlapping the second pad area among the conductive balls.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 5, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Euttum Kim, Sangwon Yeo
  • Patent number: 11837469
    Abstract: According to one embodiment, an imprint apparatus includes a first light source positioned to irradiate a substrate with light, a second light source positioned to irradiate the substrate with light, an illuminance changing portion selectively configured to change the illuminance distribution of light from the first light source on an irradiation surface on the substrate, and a controller configured to control the first light source, the second light source and the illuminance changing portion to irradiate the substrate with light from the first light source, and to subsequently irradiate the substrate with light from the second light source directly through the template.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: December 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Kazuya Fukuhara, Tetsuro Nakasugi, Masayuki Hatano
  • Patent number: 11837658
    Abstract: Disclosed is a semiconductor device, including: a substrate of a first conductivity type that is a base for the semiconductor device; a high voltage junction field effect transistor, JFET, over the substrate, wherein the JFET including a plurality of parallel conductive layers; and a first conductive layer of the second conductivity type of the parallel conductive layers stretching over the substrate. On top of the first conductive layer of the second conductivity type is arranged a plurality of layers forming the parallel conductive layers with channels formed by a plurality of doped epitaxial layers of the second conductivity type with a plurality of gate layers of the first conductivity type on both sides thereof; wherein a lowermost layer of the first conductivity type is arranged in the form of consecutive dots with different lengths and distances between them.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 5, 2023
    Assignee: K. EKLUND INNOVATION
    Inventors: Klas-HÃ¥kan Eklund, Lars Vestling
  • Patent number: 11823953
    Abstract: Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: November 21, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11817476
    Abstract: A semiconductor device includes a semiconductor layer having a first surface in which a plurality of trenches each extending along a first direction are arranged along a second direction perpendicular to the first direction, a first electrode on a second surface of the semiconductor layer, a second electrode on the first surface of the semiconductor layer, and a control electrode inside at least one of the trenches. The plurality of trenches includes first, second, and third trenches. The first and second trenches are connected to each other via a first connector at an end in the first direction of each of the first and second trenches. The third trench extends beyond the end of each of the first and second trenches along the first direction.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 14, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kotaro Zaima, Yukie Nishikawa, Emiko Adachi
  • Patent number: 11805677
    Abstract: A display substrate and a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate, a first electrode, a light-emitting functional layer, and a second electrode. The light-emitting functional layer includes a first functional layer and a second functional layer, an orthographic projection of an edge of the second functional layer on the base substrate is within an orthographic projection of an edge of the first functional layer on the base substrate, and an area of an orthographic projection of the second functional layer on the base substrate is smaller than an area of an orthographic projection of the first functional layer on the base substrate; and the second electrode covers and is in contact with at least one side surface of the light-emitting functional layer and a portion of a surface of the light-emitting functional layer away from the base substrate.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: October 31, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chao Pu, Shengji Yang, Pengcheng Lu, Kuanta Huang, Junbo Wei, Li Liu
  • Patent number: 11791312
    Abstract: Monolithic microwave integrated circuits (MMICs) with backside interconnects for fanout-style packaging are disclosed. Fanout-style packaging, such as fanout wafer (FOWLP) or fanout panel-level packaging (FOPLP), facilitates a high density package for MMICs. However, the fanout-style packaging may produce undesired electromagnetic (EM) coupling between a MMIC die and metal features in a redistribution layer (RDL) of the FOW/PLP package and/or a next higher assembly (NHA). In an exemplary aspect, a circuit package according to this disclosure includes the MMIC die and an RDL. The MMIC includes a chip side with components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 17, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Andrew Arthur Ketterson, Christo Pavel Bojkov
  • Patent number: 11791384
    Abstract: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: October 17, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Junya Yaita, Junji Kotani, Atsushi Yamada, Kozo Makiyama
  • Patent number: 11791323
    Abstract: A light emitting display device includes: a display element layer having light emitting elements; a first sub-pixel including a first light emitting element from among the plurality of light emitting elements in a first sub-pixel area of the display element layer; a second sub-pixel including a second light emitting element from among the plurality of light emitting elements in a second sub-pixel area of the display element layer; a third sub-pixel including a third light emitting element from among the plurality of light emitting elements in a third sub-pixel area of the display element layer; a partition wall between the first, second, and third sub-pixels and over an insulating layer, covering the first, second, and third light emitting elements; a first color conversion layer over the insulating layer in the first sub-pixel area and surrounded by the partition wall; and a first color filter over the first color conversion layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Duk Sung Kim
  • Patent number: 11788003
    Abstract: A semiconductor nanoparticle includes a core and a shell covering a surface of the core. The shell has a larger bandgap energy than the core and is in heterojunction with the core. The semiconductor nanoparticle emits light when irradiated with light. The core is made of a semiconductor that contains M1, M2, and Z. M1 is at least one element selected from the group consisting of Ag, Cu, and Au. M2 is at least one element selected from the group consisting of Al, Ga, In and Tl. Z is at least one element selected from the group consisting of S, Se, and Te. The shell is made of a semiconductor that consists essentially of a Group 13 element and a Group 16 element.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: October 17, 2023
    Assignees: OSAKA UNIVERSITY, NATIONAL UNIVERSITY CORPORATION TOKAI NATIONAL HIGHER EDUCATION AND RESEARCH SYSTEM, NICHIA CORPORATION
    Inventors: Susumu Kuwabata, Taro Uematsu, Kazutaka Wajima, Tsukasa Torimoto, Tatsuya Kameyama, Daisuke Oyamatsu, Kenta Niki
  • Patent number: 11784248
    Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: October 10, 2023
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes
  • Patent number: 11784071
    Abstract: A process condition measurement wafer assembly is disclosed. In embodiments, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top substrate and bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse voltage potentials across the bottom substrate and the top substrate.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 10, 2023
    Assignee: KLA Corporation
    Inventors: Farhat A. Quli, Andrew Nguyen, James Richard Bella
  • Patent number: 11777058
    Abstract: A light-emitting device (LED) includes a first semiconductor layer, a second semiconductor layer facing the first semiconductor layer, an insulating layer arranged to at least partially surround outer surfaces of the first semiconductor layer and the second semiconductor layer, and a first ligand bonded to a surface of the insulating layer and a second ligand bonded to the first ligand.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 3, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yunku Jung, Changhee Lee, Yunhyuk Ko, Dukki Kim, Jongwon Park, Jaekook Ha
  • Patent number: 11774995
    Abstract: A two-wire load control device may be configured to compute an accurate estimate of real-time power consumption by a load that is electrically connected to, and controlled by, the two-wire load control device. The load control device may be adapted to measure a voltage drop across the device during a first portion of a half-cycle of an AC waveform provided to the device. The device may be further configured to estimate a voltage drop across the load during the second portion of the half-cycle. The estimated voltage drop may be based on the measured voltage drop. The device may be further configured to measure a current supplied to the load during a second portion of the half-cycle. The device may be configured to estimate power consumed by the load based on the measured current and the estimated voltage drop.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 3, 2023
    Assignee: Lutron Technology Company LLC
    Inventors: Matthew Robert Blakeley, William Zotter